Michael Xuan Ho

US Patent:

58674217, Feb 2, 1999

Filed:

Oct 28, 1997

Appl. No.:

8/958942

Inventors:

Michael Ho - Houston TX
Scott Smith - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365149

Abstract:

An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply. In one embodiment, the large on-chip capacitor is a storage/filter capacitor (12) for a boosted high voltage supply (VPP), and the capacitive voltage reference is a memory cell reference voltage (VPLT) which is also connected to a reference plate of memory cell capacitors (28) of the memory cells (20) in the memory array.

US Patent:

6088293, Jul 11, 2000

Filed:

Sep 3, 1999

Appl. No.:

9/390568

Inventors:

Michael Duc Ho - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800

US Classification:

365233

Abstract:

A memory circuit is designed with a memory array (113, 115, 117, 119) having a plurality of banks. Each bank is addressable in response to a bank address signal (102), and each bank arranged in rows and columns of memory cells. Each of plural data leads (122) corresponds to a bank. Each data lead is selectively connected to a column of memory cells by a respective select transistor. A first decode circuit (501) has at least one input and one output terminal. The output terminal (525) is coupled to a control gate of at least one of the select transistors. Each of a plurality of second decode circuits (231) corresponds to a respective bank. Each second decode circuit has a memory element (423, 425, 428)), a plurality of input terminals and at least one output terminal. One second decode circuit input terminal (227) is coupled to receive a first address signal. Another second decode circuit input terminal (229) is coupled to receive the bank address signal.

US Patent:

62429361, Jun 5, 2001

Filed:

Aug 3, 1999

Appl. No.:

9/366232

Inventors:

Michael Duc Ho - Houston TX
Scott E. Smith - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3126

US Classification:

324765

Abstract:

A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).