Michael P Houston

US Patent:

7791324, Sep 7, 2010

Filed:

Mar 31, 2008

Appl. No.:

12/080263

Inventors:

Gustavo James Mehas - Sunnyvale CA, US
Naveen Jain - Panipat, IN
Jayant Vivrekar - San Jose CA, US
Michael Jason Houston - Cary NC, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G05F 1/00

US Classification:

323283, 323224

Abstract:

A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.

US Patent:

8120336, Feb 21, 2012

Filed:

Sep 3, 2010

Appl. No.:

12/875938

Inventors:

Gustavo James Mehas - Sunnyvale CA, US
Naveen Jain - Panipat, IN
Jayant Vivrekar - San Jose CA, US
Michael Jason Houston - Cary NC, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G05F 1/613

US Classification:

323224, 323283

Abstract:

A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator and being operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal and includes a synchronous output switch having a phase node therebetween controlled by the gate driver, and also including regulator input current measurement circuitry. The regulator input current measurement circuitry includes a circuit that provides a signal representative of at least one phase node timing parameter. A sensing circuit is operable to sense inductor or output current provided by the regulator. A calculation circuit is coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current from the phase node timing parameters and the inductor or output current.

US Patent:

8228049, Jul 24, 2012

Filed:

Jul 10, 2009

Appl. No.:

12/501204

Inventors:

Weihong Qiu - San Jose CA, US
Bogdan Duduman - Raleigh NC, US
Jason Lin - San Chun, TW
Michael Jason Houston - Cary NC, US
Doug Mattingly - Bahama NC, US

Assignee:

Intersil Americas LLC - Milpitas CA

International Classification:

G05F 1/575
G05F 1/59

US Classification:

323272, 323284

Abstract:

A control circuit for generating a control signal to add phases to a multiphase voltage regulator. The control circuit includes an input for receiving an error correction voltage from an error amplifier of the multiphase voltage regulator and at least one output for providing a PWM control signal. Control circuitry generates at least one PWM control signal to add a phase to the multiphase voltage regulator responsive to a determination that the error correction voltage has exceeded a threshold level.

US Patent:

8607247, Dec 10, 2013

Filed:

Nov 3, 2011

Appl. No.:

13/288833

Inventors:

Lee W. Howes - Santa Clara CA, US
Benedict R. Gaster - Santa Cruz CA, US
Michael C. Houston - Cupertino CA, US
Michael Mantor - Orlando FL, US
Mark Leather - Los Gatos CA, US
Norman Rubin - Cambridge MA, US
Brian D. Emberling - San Mateo CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/46
G06F 1/04
G06F 1/12
G06F 7/00

US Classification:

718106, 718101, 718107, 718108, 713375, 713400, 707610, 707613, 707620, 707624

Abstract:

Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

US Patent:

20110173629, Jul 14, 2011

Filed:

Jul 29, 2010

Appl. No.:

12/846222

Inventors:

Michael HOUSTON - Cupertino CA, US
Stanislaw Skowronek - New York NY, US
Elaine Poon - Richmond Hill, CA
Brian Emberling - Palo Alto CA, US

International Classification:

G06F 9/52

US Classification:

718106

Abstract:

A method of processing threads is provided. The method includes receiving a first thread that accesses a memory resource in a current state, holding the first thread, and releasing the first thread based responsive to a final thread that accesses the memory resource in the current state has been received.

US Patent:

20130263144, Oct 3, 2013

Filed:

Mar 29, 2013

Appl. No.:

13/853504

Inventors:

Michael Clair Houston - Cupertino CA, US
Keith Lowery - Bothell WA, US
Newton Cheung - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/48

US Classification:

718102

Abstract:

Embodiments described herein include a system, a computer-readable medium and a computer-implemented method for processing a system call (SYSCALL) request. The SYSCALL request from an invisible processing device is stored in a queueing mechanism that is accessible to a visible processing device, where the visible processing device is visible to an operating system and the invisible processing device is invisible to the operating system. The SYSCALL request is processed using the visible processing device, and the invisible processing device is notified using a notification mechanism that the SYSCALL request was processed.

US Patent:

20130327734, Dec 12, 2013

Filed:

Jun 7, 2013

Appl. No.:

13/913253

Inventors:

Tina Ting-Yuan Wang - Cupertino CA, US
Chih-Cheng Tai - Campbell CA, US
Michael Clair Houston - Cupertino CA, US

International Classification:

A47F 7/00

US Classification:

211 594, 211 8515

Abstract:

Embodiments of the present invention are directed to storage systems for milk bags. A storage system for milk bags receives milk bags and management of the stored milk bags. The milk bags are stored in compartments for easy storage and retrieval.

US Patent:

20220255537, Aug 11, 2022

Filed:

Jun 11, 2021

Appl. No.:

17/345317

Inventors:

- Milpitas CA, US
Chun Cheung - Milpitas CA, US
Michael Jason Houston - Cary NC, US
Mehul Shah - Cary NC, US

Assignee:

Renesas Electronics America Inc. - Milpitas CA

International Classification:

H03K 3/012
H03K 17/687

Abstract:

Systems, apparatuses, and methods for charging a bootstrap capacitor of a device during low power states are described. In an example, an apparatus can include a controller configured to enable a low power state of the device. The device can include a high side switching element and a low side switching element. The controller can, in response to the low power state of the device being enabled, operate the low side switching element of the device to charge the bootstrap capacitor of the device. The controller can, in response to the low power state of the device being enabled and a level of a control signal being a first level, activate the low side switching element to charge the bootstrap capacitor of the device.