Michael L Hutton

US Patent:

6407576, Jun 18, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/516921

Inventors:

Tony Ngai - Campbell CA
Bruce Pedersen - San Jose CA
James Schleicher - Santa Clara CA
Wei-Jen Huang - Burlingame CA
Michael Hutton - Palo Alto CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA
Peter J. Kazarian - Cupertino CA
Andrew Leaver - Palo Alto CA
David W. Mendel - Sunnyvale CA
Jim Park - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

6429681, Aug 6, 2002

Filed:

Feb 9, 2001

Appl. No.:

09/781056

Inventors:

Michael D. Hutton - Mountain View CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38

Abstract:

A programmable logic device has registers (âre-timing registersâ) associated with interconnection conductors. The re-timing registers are in addition to registers that are conventionally associated with other device elements such as logic and memory cells. Programmable links enable optional data paths through the re-timing registers between disconnected segments of interconnection conductors. Re-timing techniques for optimization of circuit designs seeking to minimize the longest register-to-register path can include positioning of re-timing registers on interconnection conductors. Long interconnection conductors can be used in data paths between device elements with only short segments of interconnection conductors contributing to critical path lengths.

US Patent:

6747480, Jun 8, 2004

Filed:

Jul 12, 2002

Appl. No.:

10/195209

Inventors:

Sinan Kaptanoglu - Belmont CA
Michael D. Hutton - Mountain View CA
James Schleicher - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e. g. , inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.

US Patent:

6894533, May 17, 2005

Filed:

Jun 9, 2003

Appl. No.:

10/458431

Inventors:

Tony Ngai - Campbell CA, US
Bruce Pedersen - San Jose CA, US
James Schleicher - Santa Clara CA, US
Wei-Jen Huang - Burlingame CA, US
Michael Hutton - Palo Alto CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US
Peter J. Kazarian - Cupertino CA, US
Andrew Leaver - Palo Alto CA, US
David W. Mendel - Sunnyvale CA, US
Jim Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/177

US Classification:

326 41, 326 39, 326 40

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

6977520, Dec 20, 2005

Filed:

Aug 13, 2002

Appl. No.:

10/219085

Inventors:

Michael D. Hutton - Mountain View CA, US
Richard G. Cliff - Los Altos CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/173

US Classification:

326 38, 326 46

Abstract:

Programmable logic device interconnection resources include bus wires. A bus wire provides a programmable signal path across the programmable logic device from several logic device outputs to several other logic device inputs. Serializing circuitry multiplexes multiple device output signals and drives time-multiplexed data signals on the bus wires. Bus registers placed at the ends of bus wires register or buffer the data signals transmitted over the bus wires. The registered signals are passed on to deserializing circuitry for demultiplexing data signals to provide parallel device input signals. The bus registers, and the serializing/deserializing circuitry are clocked at a rate faster than the device system clock to schedule the use of the bus wires for transmission of multiple device input/output signals over the bus wires within a system clock cycle.

US Patent:

6989689, Jan 24, 2006

Filed:

May 24, 2004

Appl. No.:

10/852858

Inventors:

Tony Ngai - Campbell CA, US
Bruce Pedersen - San Jose CA, US
James Schleicher - Santa Clara CA, US
Wei-Jen Huang - Burlingame CA, US
Michael Hutton - Palo Alto CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US
Peter J. Kazarian - Cupertino CA, US
Andrew Leaver - Palo Alto CA, US
David W. Mendel - Sunnyvale CA, US
Jim Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

7010777, Mar 7, 2006

Filed:

Mar 22, 2004

Appl. No.:

10/807360

Inventors:

Michael Hutton - Mountain View CA, US
Andy L. Lee - San Jose CA, US
Rahul Saini - Union City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 12, 716 16, 716 17, 326 41

Abstract:

Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.

US Patent:

7093219, Aug 15, 2006

Filed:

Nov 20, 2003

Appl. No.:

10/718978

Inventors:

Michael D. Hutton - Mountain View CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 6

Abstract:

Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the graph is assigned a binary edge mask, each bit of which indicates whether it is reachable from a source or destination type relevant to user specified timing constraints. A timing analysis tool then performs multiple depth-first search operations to compute delays along time critical paths relevant to the user specified timing constraints. Because each edge contains an edge mask to indicate whether it connects to a particular source or destination point, the timing analysis tool does not analyze areas of the graph that do not lead to a relevant source or destination point. These techniques prevent the timing analysis tool from analyzing paths in the graph that are not relevant to the analysis of the time critical paths.