Michael K Jensen

US Patent:

7558939, Jul 7, 2009

Filed:

Mar 8, 2005

Appl. No.:

11/075041

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711205, 711206, 711207

Abstract:

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

US Patent:

7925859, Apr 12, 2011

Filed:

Jun 30, 2009

Appl. No.:

12/495375

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711205, 711206, 711207, 711122, 711E12016, 711E12061, 711136

Abstract:

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

US Patent:

8078840, Dec 13, 2011

Filed:

Dec 30, 2008

Appl. No.:

12/346652

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/46

US Classification:

712205, 712 E9053

Abstract:

A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority.

US Patent:

20060179276, Aug 10, 2006

Filed:

Mar 22, 2005

Appl. No.:

11/087063

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 9/40

US Classification:

712205000

Abstract:

A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.

US Patent:

20090048436, Feb 19, 2009

Filed:

Aug 15, 2007

Appl. No.:

11/893614

Inventors:

Keith Anderson - Mass Beach CA, US
Michael Jensen - Los Gatos CA, US
Ronald W. Davis - Palo Alto CA, US
Charles K. Brush - Whitefish Bay WI, US
Kaizhang He - Whitefish Bay WI, US

International Classification:

C07H 21/00

US Classification:

536 253

Abstract:

The present invention provides a method of synthesizing phosphoramidite linkers that are useful for the production of synthesizing two or more oligonucleotides in tandem. The inventive linker has the following desirable properties: (i) enhanced stability to alkali conditions versus the linkers previously published, (ii) cleaves to produce 5′ and 3′ ends that are fully biologically compatible, (iii) cleaves completely under conditions that are already used in cleavage/deprotection processes so it is fully compatible with conditions that are common in laboratories and does not require additives that necessitate further purification after cleavage, (iv) integrates easily onto commercially available synthesizers because it is compatible with standard coupling chemistry, and (v) is compatible with DNA, RNA, forward, reverse, and LNA, synthesis chemistries. In addition, the inventive linkers may be coupled to a solid support. Thus, the inventive linkers provide a significant advancement in the state of the art.

US Patent:

20120221838, Aug 30, 2012

Filed:

Feb 24, 2012

Appl. No.:

13/404350

Inventors:

Soumya BANERJEE - San Jose CA, US
Gideon D. INTRATER - Sunnyvale CA, US
Michael Gottlieb JENSEN - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712227, 712E09016, 712E09045

Abstract:

The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.

US Patent:

20140350235, Nov 27, 2014

Filed:

May 18, 2014

Appl. No.:

14/280609

Inventors:

Michael S. Akhras - Stockholm, SE
Michael A. Jensen - Los Gatos CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

C07H 1/02
H01F 13/00
B01J 19/08

US Classification:

536 2534, 42218601, 335284

Abstract:

A novel method for attaching oligonucleotides to a paramagnetic solid support is disclosed. Conventional methods of attachment require that oligonucleotides be pre-synthesized with specific end modifications, which is laborious and expensive. Instead, we attached oligonucleotides to paramagnetic beads by direct synthesis of the oligonucleotides on the surface of the beads. An external magnet was used to hold the paramagnetic beads in place during solid-phase synthesis. A magnetic force was applied directly to the beads to prevent their loss, in particular, during reagent purge-to-waste steps that involved high-pressure drain or vacuum. This method can be adapted for use in any laboratory working with conventional synthesis automation, and can be employed, for example, with single columns and multi-well titer plates.