Michael Wm Jensen

US Patent:

7600100, Oct 6, 2009

Filed:

Dec 6, 2006

Appl. No.:

11/567290

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/00
G06F 13/24

US Classification:

712224, 712244, 710262

Abstract:

An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are to communicate with privileged control registers. The instructions designate which of a plurality of privileged architecture registers is to be modified, which bit fields within the designated privileged architecture register is to be modified, and whether the designated bit fields are to be set or cleared. An instruction atomically sets or clears bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

US Patent:

7634638, Dec 15, 2009

Filed:

Oct 22, 2002

Appl. No.:

10/279210

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/00
G06F 13/24

US Classification:

712224, 712244, 710262

Abstract:

An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

US Patent:

7657891, Feb 2, 2010

Filed:

Feb 4, 2005

Appl. No.:

11/051979

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US
Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Sanjay Vishin - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/46
G06F 9/40

US Classification:

718102, 712216, 712219

Abstract:

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.

US Patent:

7664936, Feb 16, 2010

Filed:

Feb 4, 2005

Appl. No.:

11/051998

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US
Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Sanjay Vishin - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/50

US Classification:

712214, 712219, 718103

Abstract:

An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.

US Patent:

8151268, Apr 3, 2012

Filed:

Jan 8, 2010

Appl. No.:

12/684564

Inventors:

Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Sanjay Vishin - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/46
G06F 15/00

US Classification:

718102, 712216, 712219, 712228

Abstract:

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.

US Patent:

8190865, May 29, 2012

Filed:

Oct 9, 2009

Appl. No.:

12/576942

Inventors:

Michael G. Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/00

US Classification:

712244

Abstract:

An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

US Patent:

8329882, Dec 11, 2012

Filed:

Feb 18, 2010

Appl. No.:

12/708506

Inventors:

Christina D. Smolke - Stanford CA, US
Yvonne Y. Chen - Pasadena CA, US
Michael C. Jensen - Sierra Madre CA, US

Assignee:

California Institute of Technology - Pasadena CA
City of Hope - Duarte CA

International Classification:

C07H 21/02
C07H 21/04
C12N 5/00
C12N 5/02

US Classification:

536 231, 536 241, 536 245, 435375

Abstract:

The present application relates to nucleic acids that encode a RNA switch responsive to a ligand that can control the expression of a gene product that affects the cell fate determination of a mammalian cell are provided. In some embodiments, the system can be used to control the proliferation or activation of mammalian cells in response to a ligand that can be provided exogenously to the mammalian cell or can be produced by the mammalian cell. The system can be used to promote the growth or proliferation of human T cells in response to an exogenous ligand applied to the cells. In one embodiment, the system detects the ligand through a RNA aptamer that modulates expression of a gene product through activation or inactivation of a ribozyme that modulates expression of the gene product.

US Patent:

20060179194, Aug 10, 2006

Filed:

Mar 22, 2005

Appl. No.:

11/087064

Inventors:

Michael Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 13/00

US Classification:

710111000

Abstract:

A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requester. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.