Michael Sheldon Jensen

US Patent:

7558939, Jul 7, 2009

Filed:

Mar 8, 2005

Appl. No.:

11/075041

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711205, 711206, 711207

Abstract:

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

US Patent:

7600100, Oct 6, 2009

Filed:

Dec 6, 2006

Appl. No.:

11/567290

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/00
G06F 13/24

US Classification:

712224, 712244, 710262

Abstract:

An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are to communicate with privileged control registers. The instructions designate which of a plurality of privileged architecture registers is to be modified, which bit fields within the designated privileged architecture register is to be modified, and whether the designated bit fields are to be set or cleared. An instruction atomically sets or clears bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

US Patent:

7634638, Dec 15, 2009

Filed:

Oct 22, 2002

Appl. No.:

10/279210

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/00
G06F 13/24

US Classification:

712224, 712244, 710262

Abstract:

An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

US Patent:

7653701, Jan 26, 2010

Filed:

Feb 23, 2001

Appl. No.:

09/792371

Inventors:

William D. Burns - Meridian ID, US
Michael W. Jensen - Caldwell ID, US
Loren R. Mart - Meridian ID, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 15/16

US Classification:

709217, 709202, 709203, 709227

Abstract:

A network device configured to be coupled to a network includes a plurality of input/output ports configured to be coupled to a plurality of input sources and receive a plurality of input data items. The network device includes an input device for entering destination information and output format information for each of the plurality of input data items. An interface bridge coupled to the plurality of input/output ports receives the plurality of input data items from the plurality of input/output ports and outputs the plurality of input data items using a single output protocol. A controller coupled to the interface bridges receives the plurality of input data items. The controller automatically converts each of the input data items to an output data item based on the entered destination and output format information, and automatically outputs the output data items to the network.

US Patent:

7657891, Feb 2, 2010

Filed:

Feb 4, 2005

Appl. No.:

11/051979

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US
Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Sanjay Vishin - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/46
G06F 9/40

US Classification:

718102, 712216, 712219

Abstract:

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions of other threads to continue executing. The execution pipeline communicates to the scheduler which thread caused the stalling event, and the scheduler stops dispatching instructions for the thread until the stalling condition terminates. In one embodiment, the execution pipeline only flushes the thread including the instruction that caused the event. In one embodiment, the execution pipeline stalls rather than flushing if the thread is the only runnable thread. In one embodiment, the processor includes skid buffers to which the flushed instructions are rolled back so the instruction fetch pipeline need not be flushed, only the execution pipeline.

US Patent:

7664936, Feb 16, 2010

Filed:

Feb 4, 2005

Appl. No.:

11/051998

Inventors:

Michael Gottlieb Jensen - Sunnyvale CA, US
Darren M. Jones - Los Altos CA, US
Ryan C. Kinter - Sammamish WA, US
Sanjay Vishin - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/50

US Classification:

712214, 712219, 718103

Abstract:

An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.

US Patent:

7925859, Apr 12, 2011

Filed:

Jun 30, 2009

Appl. No.:

12/495375

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US
Ryan C. Kinter - Sammamish WA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711205, 711206, 711207, 711122, 711E12016, 711E12061, 711136

Abstract:

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

US Patent:

8078840, Dec 13, 2011

Filed:

Dec 30, 2008

Appl. No.:

12/346652

Inventors:

Soumya Banerjee - San Jose CA, US
Michael Gottlieb Jensen - Sunnyvale CA, US

Assignee:

MIPS Technologies, Inc. - Sunnyvale CA

International Classification:

G06F 9/46

US Classification:

712205, 712 E9053

Abstract:

A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority.