Michael J Keith

US Patent:

58570888, Jan 5, 1999

Filed:

Sep 18, 1995

Appl. No.:

8/529908

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

395386

Abstract:

Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing--an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources--a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

US Patent:

54521017, Sep 19, 1995

Filed:

Dec 11, 1992

Appl. No.:

7/989602

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 141

US Classification:

358426

Abstract:

Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing--an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources--a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

US Patent:

53251245, Jun 28, 1994

Filed:

Dec 22, 1992

Appl. No.:

7/995121

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 713

US Classification:

348391

Abstract:

In a method and apparatus for scalably decoding a sequence of encoded digital video frames on a digital processor, an interpolation level is determined in accordance with the processing power of the digital processor. An encoded frame is selected from the sequence for decoding. If the interpolation level is greater than a predetermined threshold, then a scalably decoded frame is formed by interpolating the selected frame in accordance with a first pixel depth level. If the interpolation level is not greater than the predetermined threshold, then a scalably decoded frame is formed by interpolating the selected frame in accordance with a second pixel depth level, the second pixel depth level having fewer bits than the first pixel depth level.

US Patent:

53251261, Jun 28, 1994

Filed:

Apr 1, 1992

Appl. No.:

7/861227

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 713

US Classification:

348418

Abstract:

A bitstream representative of at least one digital video image is decoded in real time by providing a code-book index from the bitstream, applying the code-book index to an index table to determine an index value, and comparing the index value to a first predetermined threshold. If the index value is greater than the predetermined threshold, then at least one current pixel is determined by copying a corresponding previous pixel into the location of at least one current pixel; otherwise the index value is applied to a vector table to determine at least one vector value and a current pixel is determined from the vector value and a corresponding previous pixel. A digital video image is encoded in real time by selecting at least one pixel for encoding and determining at least one difference value between the selected pixel and at least one corresponding previous pixel. An index value corresponding to the location in a first table of the difference value is calculated. If the index value is equal to a first predetermined value then a run-length counter is implemented by a second predetermined value and the process is repeated until the index value is not equal to the first predetermined value.

US Patent:

52805719, Jan 18, 1994

Filed:

Feb 3, 1992

Appl. No.:

7/829919

Inventors:

Michael Keith - Holland PA
Yaron Minsky - Kendall Park NJ

Assignee:

Intel Corporation - Hillsboro OR

International Classification:

G06F 1562

US Classification:

395143

Abstract:

A method and apparatus for creating computer generated lines using a single or multiple instruction multiple data processor in conjunction with a modified version of Bresenham's line drawing algorithm wherein the speed of the operation is enhanced by allowing the processor to perform its memory writes in page mode.

US Patent:

54185688, May 23, 1995

Filed:

Aug 1, 1994

Appl. No.:

8/283824

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 726

US Classification:

348390

Abstract:

A method and apparatus for scalably decoding a sequence of encoded digital video frames with a digital processor. A frame discard interval is determined in accordance with the processing power of the digital processor and a counter is initialized. A frame is selected from the sequence for decoding. The selected frame is decoded and the counter is incremented. If the counter is less than the discard interval then the process is repeated; otherwise, at least one subsequent frame from the sequence is replaced with a sync frame which is thereafter decoded.

US Patent:

53631390, Nov 8, 1994

Filed:

Dec 22, 1992

Appl. No.:

7/995122

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 7137

US Classification:

348415

Abstract:

In a method and apparatus for scalably encoding in real time a sequence of digital video frames, a target digital processor class to be used for decoding the sequence is selected. A stillperiod value is selected in accordance with the selected target digital processor class. Every Nth frame of the sequence is then encoded as a still frame, and all other frames are encoded using interframe difference values, wherein N is equal to the stillperiod value.

US Patent:

55598315, Sep 24, 1996

Filed:

Oct 23, 1995

Appl. No.:

8/546619

Inventors:

Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 166
H03M 740
H03M 700

US Classification:

375240

Abstract:

A variable-length decoder system decodes a variable-length code having different code prefixes in an input bit stream. A code prefix is located in the bit stream and used to determine a number of bits to be selected from the input bit stream according to an access of a code book. Additionally, a pointer, directing access to a different code book, may also be indicated by the access of the first code book according to the located code prefix. A determination is made in this decoder system whether to perform the operation of determining a number of bits to be selected from the input stream or accessing a second code prefix table. If the code value is valid, the number of bits is selected and appended to the code prefix to form a code word which is later decoded by the system of the present invention. If another table is indicated a further code prefix is located in the input stream and the further lookup table is accessed in accordance with the further code prefix.