Michael A Lane

US Patent:

6359233, Mar 19, 2002

Filed:

Oct 26, 1999

Appl. No.:

09/426758

Inventors:

Steven C. Joy - Portland OR
Michael J. Lane - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 111

US Classification:

174255, 174250, 174256, 361737, 361739, 361774, 361779, 361792, 428901

Abstract:

Disclosed is a printed circuit board multipack, having a plurality of printed circuit boards (for example, a plurality of PCI compliant cards) provided using a common web of substrate material for a printed circuit board. Also disclosed is printed circuit board multipack structure, from which the multipack is formed, and individual printed circuit boards formed from the multipack, and methods of manufacture of each. Printed circuit board structures of the multipack have an internal edge, spaced from the periphery of the web, that is bevelled, and have conductive fingers, e. g. , with an electrodeposited gold uppermost layer, extending to the internal edge. The multipack structure includes a common bus bar running adjacent the inner boundary of the printed circuit board structures, and conductive extensions from a conductive base layer of the conductive fingers to the bus bar. Due to the conductive extensions and common bus bar, electrode-position of the gold for the conductive fingers can easily be performed. In forming the multipack from the multipack structure, the structure is bevelled at the inner boundary, using a circular bevelling blade, to both provide the bevelled inner edge and remove the common bus bar and conductive extensions.

US Patent:

6764774, Jul 20, 2004

Filed:

Jun 19, 2002

Appl. No.:

10/174748

Inventors:

Alfred Grill - White Plains NY
Michael Lane - Cortlandt Manor NY
Vishnubhai V. Patel - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2912

US Classification:

428641, 428620, 428689, 428698, 428702, 428704, 257759, 257760, 257762, 257763, 257774, 257751, 438623, 438624, 438628, 438680

Abstract:

A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (âBEOLâ) wiring structure in which the adhesion between different dielectric is enhanced by an intermediate a-Si, a-Ge, or alloys thereof bonding layer. The thin a-Si, a-Ge, or alloys thereof layer may be hydrogenated or non-hydrogenated, or even partially oxidized.

US Patent:

6787912, Sep 7, 2004

Filed:

Apr 26, 2002

Appl. No.:

10/132173

Inventors:

Michael Lane - Cortlandt Manor NY
Fenton Read McFeely - Ossining NY
Conal Murray - Yorktown Heights NY
Robert Rosenberg - Cortlandt Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257762, 257750, 438628

Abstract:

A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.

US Patent:

6812143, Nov 2, 2004

Filed:

Oct 24, 2002

Appl. No.:

10/279057

Inventors:

Michael Lane - Cortlandt Manor NY
Fenton Read McFeely - Ossining NY
Conal Murray - Yorktown Heights NY
Robert Rosenberg - Cortlandt Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438643, 438653, 438656, 438678, 438687

Abstract:

The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

US Patent:

6974531, Dec 13, 2005

Filed:

Oct 15, 2002

Appl. No.:

10/269956

Inventors:

Panayotis Andricacos - Croton on Hudson NY, US
Hariklia Deligianni - Tenafly NJ, US
Wilma Jean Horkans - Ossining NY, US
Keith T. Kwietniak - Highlandfalls NY, US
Michael Lane - Cortlandt Manor NY, US
Sandra G. Malhotra - Beacon NY, US
Fenton Read McFeely - Ossining NY, US
Conal Murray - Yorktown Heights NY, US
Kenneth P. Rodbell - Sandy Hook CT, US
Philippe M. Vereecken - Sleepy Hollow NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25D005/18
B32B015/00

US Classification:

205102, 205104, 205157, 205261, 205291, 205640, 428615, 428620, 428655, 428656, 428674, 428926

Abstract:

A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

US Patent:

7084479, Aug 1, 2006

Filed:

Dec 8, 2003

Appl. No.:

10/731377

Inventors:

Stefanie Ruth Chiras - Peekskill NY, US
Matthew Earl Colburn - Hopewell Junction NY, US
Timothy Joseph Dalton - Ridgefield CT, US
Jeffrey Curtis Hedrick - Montvale NJ, US
Elbert Emin Huang - Tarrytown NY, US
Kaushik Arun Kumar - Beacon NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Kelly Malone - Poughkeepsie NY, US
Chandrasekhar Narayan - Hopewell Junction NY, US
Satyanarayana Venkata Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Robert Rosenburg - Cortlandt Manor NY, US
Christy Sensenich Tyberg - Mahopac NY, US
Roy RongQing Yu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/00
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257522, 257758, 257 21581, 257 21573, 257 23013

Abstract:

In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

US Patent:

7119018, Oct 10, 2006

Filed:

Jul 9, 2004

Appl. No.:

10/887087

Inventors:

Michael W. Lane - Cortlandt Manor NY, US
Stefanie R. Chiras - Peekskill NY, US
Terry A. Spooner - New Fairfield CT, US
Robert Rosenberg - Cortlandt Manor NY, US
Daniel C. Edelstein - White Plains NY, US

Assignee:

International Buisness Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438686, 438687, 438E23005

Abstract:

A conducting material comprising: a conducting core region comprising copper and from 0. 001 atomic percent to 0. 6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

US Patent:

7276787, Oct 2, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729254

Inventors:

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

US Classification:

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

Abstract:

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.