Michael K Lane

US Patent:

6764774, Jul 20, 2004

Filed:

Jun 19, 2002

Appl. No.:

10/174748

Inventors:

Alfred Grill - White Plains NY
Michael Lane - Cortlandt Manor NY
Vishnubhai V. Patel - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2912

US Classification:

428641, 428620, 428689, 428698, 428702, 428704, 257759, 257760, 257762, 257763, 257774, 257751, 438623, 438624, 438628, 438680

Abstract:

A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (âBEOLâ) wiring structure in which the adhesion between different dielectric is enhanced by an intermediate a-Si, a-Ge, or alloys thereof bonding layer. The thin a-Si, a-Ge, or alloys thereof layer may be hydrogenated or non-hydrogenated, or even partially oxidized.

US Patent:

7276787, Oct 2, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729254

Inventors:

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

US Classification:

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

Abstract:

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

US Patent:

7405147, Jul 29, 2008

Filed:

Jan 30, 2004

Appl. No.:

10/707996

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438618, 438623, 438703

Abstract:

A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

US Patent:

7479306, Jan 20, 2009

Filed:

May 18, 2005

Appl. No.:

11/132108

Inventors:

Daniel C. Edelstein - White Plains NY, US
Stephen M. Gates - Ossining NY, US
Alfred Grill - White Plains NY, US
Michael Lane - Cortlandt Manor NY, US
Qinghuang Lin - Mt. Kisco NY, US
Robert D. Miller - San Jose CA, US
Deborah A. Neumayer - Danbury CT, US
Son Van Nguyen - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C23C 16/22

US Classification:

427447, 427452, 42725529, 427255393, 438781

Abstract:

A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CHfunctional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH]— where n is greater than or equal to 1, HC═CH, C═CH, C≡C or a [S]linkage, where n is a defined above.

US Patent:

7592685, Sep 22, 2009

Filed:

Aug 31, 2007

Appl. No.:

11/849048

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/93

US Classification:

257522, 257499

Abstract:

Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

US Patent:

7892648, Feb 22, 2011

Filed:

Jan 21, 2005

Appl. No.:

11/040778

Inventors:

Daniel C. Edelstein - White Plains NY, US
Stephen M. Gates - Ossining NY, US
Alfred Grill - White Plains NY, US
Michael Lane - Cortlandt Manor NY, US
Robert D. Miller - San Jose CA, US
Deborah A. Neumayer - Danbury CT, US
Son Van Nguyen - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 9/04

US Classification:

428447, 428446, 427578, 427588, 438788, 438789, 438790

Abstract:

A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CHfunctional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH]— where n is greater than or equal to 1, HC═CH, C═CH, C≡C or a [S]linkage, where n is a defined above.

US Patent:

7892940, Feb 22, 2011

Filed:

Sep 6, 2007

Appl. No.:

11/851123

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438421, 438618, 438703

Abstract:

Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

US Patent:

8101236, Jan 24, 2012

Filed:

Jan 16, 2009

Appl. No.:

12/355316

Inventors:

Daniel C. Edelstein - White Plains NY, US
Stephen M. Gates - Ossining NY, US
Alfred Grill - White Plains NY, US
Michael Lane - Cortlandt Manor NY, US
Qinghuang Lin - Mt. Kisco NY, US
Robert D. Miller - San Jose CA, US
Deborah A. Neumayer - Danbury CT, US
Son Van Nguyen - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C23C 16/40

US Classification:

42725529, 42725531, 42725537, 427535, 427551, 427553

Abstract:

A method of fabricating a low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided. The method includes the deposition of the dielectric material from a first precursor which is an carbosilane or an alkoxycarbosilane molecule.