Michael Y Lin

US Patent:

20110099421, Apr 28, 2011

Filed:

Aug 11, 2010

Appl. No.:

12/854490

Inventors:

Alessandro Geist - Bethesda MD, US
Thomas P. Flatley - Hungtington MD, US
Michael R. Lin - Ellicott City MD, US
David J. Petrick - Severna Park MD, US

International Classification:

G06F 11/16

US Classification:

714 10, 714E11061

Abstract:

A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit. The output interfaces include at least one serial advanced technology attachment interface and at least one space-rated balanced voltage digital interface circuit.

US Patent:

20130181809, Jul 18, 2013

Filed:

Jul 18, 2012

Appl. No.:

13/551649

Inventors:

Michael R. Lin - Ellicott City MD, US
David J. Petrick - SEVERNA PARK MD, US
ALESSANDRO GElST - BETHESDA MD, US
Thomas P. Flatley - Huntington MD, US

International Classification:

G05B 19/02

US Classification:

340 43

Abstract:

An on-board space processing system capable of processing data at more than 2500 Million Instructions Per Second on board a spacecraft is disclosed. The system may be a cube, and may include processor card and a hybrid card. The processor card may include a processor that may be programmable and reprogrammable prior to, and during, spaceflight. The hybrid card may include a field programmable gate array module that may program and reprogram the processor prior to, and during, the spaceflight.

US Patent:

20180270299, Sep 20, 2018

Filed:

Mar 16, 2017

Appl. No.:

15/461044

Inventors:

- Frederick MD, US
Michael LIN - Frederick MD, US

Assignee:

FUGUE, INC. - Frederick MD

International Classification:

H04L 29/08
H04L 12/24
H04L 12/26
G06F 9/44

Abstract:

A method for building, optimizing, and maintaining a computing infrastructure on a cloud computing environment is provided. A user provides a high-level declaration to a cloud environment operating system, specifying the details of the infrastructure that is intended to be built on the cloud. A cloud environment operating system converts the high level declaration to a lower level declaration and then to a series of instructions that can be executed by the cloud to build the desired infrastructure. The instructions can be sent to an API of a cloud service provider for execution. In order to avoid tripping an API throttle limit imposed by the cloud service provider, the cloud operating system can send a pre-determined number of commands to the API at any given time so as to avoid having the commands rejected due to exceeding the API throttle.

US Patent:

20170358877, Dec 14, 2017

Filed:

Jun 10, 2016

Appl. No.:

15/179020

Inventors:

- Washington DC, US
MICHAEL R. LIN - ELLICOTT CITY MD, US

International Classification:

H01R 12/70

Abstract:

A stacking pin alignment fixture for a stacking connector includes a substrate and a plurality of openings defined in the substrate, the plurality of openings being arranged in a predefined pattern. The predefined pattern corresponds to a pattern of a field of straight pins arranged on the stacking connector.

US Patent:

20170074909, Mar 16, 2017

Filed:

Sep 15, 2015

Appl. No.:

14/855001

Inventors:

- Washington DC, US
MICHELLE B. SCOTT - Clinton MD, US
THOMAS K. JOHNSON - Ellicott City MD, US
YUKLUN LEUNG - Silver Spring MD, US
MICHAEL R. LIN - Ellicott City MD, US

International Classification:

G01R 19/15
G01R 31/04

Abstract:

A method of safe to mate testing includes providing a file of netlist signals where each signal defines a first connection to one or more components of a unit under test, connecting a first terminal of a measuring device to a first netlist signal and connecting a second terminal of the measuring device to a second netlist signal, performing a plurality of first resistive measurements by applying power having a first polarity between the first and second netlist signals, performing at least one second resistive measurement by applying power having a second polarity to the first and second netlist signals, and recording an average of the first resistive measurements and, if the second polarity measurement yields a negative result, an indication that a reactive load is connected between the first and second netlist signals.