Michael Hang-Bun Lin

US Patent:

20110099421, Apr 28, 2011

Filed:

Aug 11, 2010

Appl. No.:

12/854490

Inventors:

Alessandro Geist - Bethesda MD, US
Thomas P. Flatley - Hungtington MD, US
Michael R. Lin - Ellicott City MD, US
David J. Petrick - Severna Park MD, US

International Classification:

G06F 11/16

US Classification:

714 10, 714E11061

Abstract:

A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit. The output interfaces include at least one serial advanced technology attachment interface and at least one space-rated balanced voltage digital interface circuit.

US Patent:

20130181809, Jul 18, 2013

Filed:

Jul 18, 2012

Appl. No.:

13/551649

Inventors:

Michael R. Lin - Ellicott City MD, US
David J. Petrick - SEVERNA PARK MD, US
ALESSANDRO GElST - BETHESDA MD, US
Thomas P. Flatley - Huntington MD, US

International Classification:

G05B 19/02

US Classification:

340 43

Abstract:

An on-board space processing system capable of processing data at more than 2500 Million Instructions Per Second on board a spacecraft is disclosed. The system may be a cube, and may include processor card and a hybrid card. The processor card may include a processor that may be programmable and reprogrammable prior to, and during, spaceflight. The hybrid card may include a field programmable gate array module that may program and reprogram the processor prior to, and during, the spaceflight.

US Patent:

49501720, Aug 21, 1990

Filed:

Oct 10, 1989

Appl. No.:

7/419405

Inventors:

John W. Anhalt - Orange CA
Edward Rudoy - Woodland Hills CA
William J. Clark - Mission Viejo CA
Michael A. Lin - Anaheim CA

Assignee:

ITT Corporation - New York NY

International Classification:

H01R 13648

US Classification:

439108

Abstract:

A connector is provided of the type that has rows of contacts, which minimizes cross talk between adjacent contacts. An interceptor plate (60, FIG. 2) which is grounded or at another controlled potential, extends along each row of contacts (34), the plate lying close to the row to provide better capacitive coupling between each contact and the plate than between contacts of the same or different rows.

US Patent:

51818558, Jan 26, 1993

Filed:

Jun 18, 1992

Appl. No.:

7/899581

Inventors:

Rene A. Mosquera - Laguna Niguel CA
Michael A. Lin - Anaheim CA

Assignee:

ITT Corporation - Secaucus NJ

International Classification:

H01R 1300

US Classification:

439 74

Abstract:

A connector system is provided that is especially useful for SCEM (small computer expandability module) systems wherein small circuit boards or "tiles" can be stacked at different positions on a small mother board, wherein each connector includes numerous very small matable contacts that must carry high frequency signals. The contacts of first and second matable connectors each have forward portions (80, FIG. 6) comprising an elongated beam (132) having a straight rear part (140) extending parallel to the mating direction (114) and having a forward part (144) with a sidewardly-projecting protuberance (146). When the connectors are mated, the protuberance of each contact engages the straight rear part of the other contact. Each connector housing includes an insulator with an upstanding support wall (91) having a plurality of grooves (122) spaced along a row of contacts, with each groove surrounding the axis (142) of each contact on three sides, except for the contact protuberance. When the connectors are mated, each support wall is inserted into a slot lying between a pair of support walls of the other connector.

US Patent:

51565544, Oct 20, 1992

Filed:

Jul 22, 1991

Appl. No.:

7/733503

Inventors:

Edward Rudoy - Woodland Hills CA
Michael A. Lin - Irvine CA

Assignee:

ITT Corporation - Secaucus NJ

International Classification:

H01R 13648

US Classification:

439108

Abstract:

A connector is provided of the type that has rows of contacts, which minimizes crosstalk between adjacent contacts. An interceptor plate (60, FIG. 2) which is grounded or at another controlled potential, extends along each row of contacts (34), the plate lying close to the row to provide better capacitive coupling between each contact and the plate than between contacts of the same or different rows. The space between each contact leg and an adjacent interceptor plate, contains a dielectric whose dielectric constant varies by no more than four per cent between 1 kHz and 100 MHz. The capacitance between each contact and an adjacent interception plate is at least three times the capacitance between adjacent contacts of a row.

US Patent:

20170358877, Dec 14, 2017

Filed:

Jun 10, 2016

Appl. No.:

15/179020

Inventors:

- Washington DC, US
MICHAEL R. LIN - ELLICOTT CITY MD, US

International Classification:

H01R 12/70

Abstract:

A stacking pin alignment fixture for a stacking connector includes a substrate and a plurality of openings defined in the substrate, the plurality of openings being arranged in a predefined pattern. The predefined pattern corresponds to a pattern of a field of straight pins arranged on the stacking connector.

US Patent:

20170074909, Mar 16, 2017

Filed:

Sep 15, 2015

Appl. No.:

14/855001

Inventors:

- Washington DC, US
MICHELLE B. SCOTT - Clinton MD, US
THOMAS K. JOHNSON - Ellicott City MD, US
YUKLUN LEUNG - Silver Spring MD, US
MICHAEL R. LIN - Ellicott City MD, US

International Classification:

G01R 19/15
G01R 31/04

Abstract:

A method of safe to mate testing includes providing a file of netlist signals where each signal defines a first connection to one or more components of a unit under test, connecting a first terminal of a measuring device to a first netlist signal and connecting a second terminal of the measuring device to a second netlist signal, performing a plurality of first resistive measurements by applying power having a first polarity between the first and second netlist signals, performing at least one second resistive measurement by applying power having a second polarity to the first and second netlist signals, and recording an average of the first resistive measurements and, if the second polarity measurement yields a negative result, an indication that a reactive load is connected between the first and second netlist signals.