Michael A Lucas

US Patent:

6493994, Dec 17, 2002

Filed:

Feb 19, 2002

Appl. No.:

09/683819

Inventors:

Michael Lucas - New Windsor NY 12553

International Classification:

E04D 13076

US Classification:

52 12, 52 11, 210477

Abstract:

A gutter assembly is formed from a series of identical sections, each between twelve and eighteen inches in length. Each section is attached to one or two adjacent sections at the ends, and the final assembly attached to the eaves, soffit, or fascia of the house in the same manner as the prior art rain gutter. Each section has a section body, with an interior surface. Within the interior surface is a water-permeable screen, disposed in close proximity to the section outer housing. A discharge handle is provided to raise the screen from the interior surface, and rotate the screen in a manner such that any debris captured by the screen will be expelled from the gutter section. The handle is accessible from the grounds by means of a rod with a hook which engages a loop at the end of the handle. Each section contains a discharge passage on each end, except that the two extreme ends of the assembly contain an outer end which is sealed off, and further contain provisions for downspouts.

US Patent:

7783994, Aug 24, 2010

Filed:

Dec 14, 2006

Appl. No.:

11/638530

Inventors:

Harold Hasely Ball - Woodbine MD, US
Michael Robert Lucas - Ellicott City MD, US
Anastasios P. Goutzoulis - Annapolis MD, US

Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 11, 716 16

Abstract:

A system and a method for providing secure and trusted application specific integrated circuits (ASICs) using three-dimensional (3D) integrated circuit (IC) integration. The method includes fabricating a plurality of sub-circuits and assembling an overall 3D ASIC device from the plurality of sub-circuits. Each sub-circuit includes a plurality of input-output (IO) pads, is fabricated with a orientation point that indicates a compass orientation of the sub-circuit, and is rotationally symmetrical. The assembling includes determining the designed sub-circuit integration order, determining the designed orientation for each sub-circuit, stacking each sub-circuit per the determined integration order, and orienting each sub-circuit per the determined orientation, and wherein function and operation of the overall 3D ASIC device is determinable only from the assembled 3D ASIC stack and not the sub-circuits. The fabricating may be performed at one or more un-trusted facilities and the assembling may be performed at a trusted facility remote from the fabricating facilities.

US Patent:

20070261791, Nov 15, 2007

Filed:

May 12, 2006

Appl. No.:

11/432437

Inventors:

Akis Goutzoulis - Annapolis MD, US
Michael Lucas - Ellicott City MD, US

International Classification:

C09J 163/00

US Classification:

156330000

Abstract:

A method of low cost, practical fabrication of 2D fiber optic bundles. The method includes stripping an end of a fiber ribbon. The stripping exposes a plurality of stripped fiber ribbon ends. The method also includes etching the stripped fiber ribbon ends and inserting the etched, stripped fiber ribbon ends into a plate. The etching reduces the diameter of stripped fiber ribbon ends. The inserting inserts all of the etched, stripped fiber ribbon ends of the fiber ribbon into the plate simultaneously. The method also includes epoxying the plate and the inserted fiber ribbon ends. The inserted fiber ribbon ends and the plate form a fiber bundle. The fiber bundle is polished.

US Patent:

45545758, Nov 19, 1985

Filed:

May 12, 1983

Appl. No.:

6/493903

Inventors:

Michael R. Lucas - Arbutus MD

Assignee:

Westinghouse Electric Corp. - Pittsburgh PA

International Classification:

H01L 2314
H01L 2310
H01L 2334

US Classification:

357 80

Abstract:

A leadless integrated circuit chip carrier apparatus and method of assembly to a printed circuit board. A plurality of castellations are provided in the perimeter walls of the carrier member and solder preforms are deformably fitted in the castellations for reflow vapor phase soldering to the printed circuit board. A spacer member is disposed between the carrier member and the printed circuit board and has a thermal coefficient of expansion matched to that of the solder. The spacer includes a high thermal conductivity planar metal portion sandwiched between an adhesive epoxy layer which facilitates assembly of the carrier to the circuit board.

US Patent:

45312850, Jul 30, 1985

Filed:

Mar 21, 1983

Appl. No.:

6/477692

Inventors:

Michael R. Lucas - Baltimore MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01R 4300
B32B 310

US Classification:

29827

Abstract:

The invention is a method for interconnecting close lead center integrated ircuit package to boards by forming the leads as follows: (1) bonding the lead frame material to a thin insulating film, and the (2) forming the leads. Next, the film base is removed selectively where connections to the package and board will be made. The lead material is then plated and formed to provide stress relief in the package-to-board interconnect. The lead frame is then attached to the package and board.