Michael Lee Mayfield

US Patent:

6446167, Sep 3, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435861

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

711122, 711 3, 711118, 711119, 711133, 711137, 711144

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

US Patent:

6446170, Sep 3, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/232239

Inventors:

Kin Shing Chan - Austin TX
Dwain Alan Hicks - Pflugerville TX
Michael John Mayfield - Austin TX
Shih-Hsiung Stephen Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711132, 711133, 711210

Abstract:

A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access.

US Patent:

6460115, Oct 1, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435865

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

711122, 711137, 711213, 712207

Abstract:

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

US Patent:

6535962, Mar 18, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/435860

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711137, 711122, 711204, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

US Patent:

6574712, Jun 3, 2003

Filed:

Apr 14, 2000

Appl. No.:

09/550180

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel M. Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711137, 711122, 711213, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

US Patent:

6578130, Jun 10, 2003

Filed:

Oct 18, 2001

Appl. No.:

09/981880

Inventors:

Brian David Barrick - Pflugerville TX
Michael John Mayfield - Austin TX
Brian Patrick Hanley - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711213, 711137, 711204

Abstract:

A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.

US Patent:

6587930, Jul 1, 2003

Filed:

Sep 23, 1999

Appl. No.:

09/404400

Inventors:

Sanjay Raghunath Deshpande - Austin TX
Peter Steven Lenk - Austin TX
Michael John Mayfield - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711144, 711145, 711122

Abstract:

A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks.

US Patent:

6915415, Jul 5, 2005

Filed:

Jan 7, 2002

Appl. No.:

10/042102

Inventors:

Michael John Mayfield - Austin TX, US
Francis Patrick O'Connell - Austin TX, US
David Scott Ray - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/30

US Classification:

712225, 712205, 711137

Abstract:

A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.