Michael J Mcmanus

Address:

1876 Frst Vw Ct, Cincinnati, OH 45233

VIN:

JTEBU14R170107639

Make:

TOYOTA

Model:

4RUNNER

Year:

2007

US Patent:

6766496, Jul 20, 2004

Filed:

Jun 3, 2002

Appl. No.:

10/162123

Inventors:

Michael J. McManus - Liberty Township OH
Billie J. Rivera - San Jose CA
Richard Talburt - Sunnyvale CA
William G. Walker - Saratoga CA
Michael A. Zampaglione - San Jose CA

Assignee:

Virtual Silicon Technology, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 1, 716 4, 716 12, 716 13, 716 14, 716 15, 716 16

Abstract:

Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

US Patent:

6839882, Jan 4, 2005

Filed:

Jun 3, 2002

Appl. No.:

10/162536

Inventors:

Michael J. McManus - Liberty Township OH, US
Billie J. Rivera - San Jose CA, US
Richard Talburt - Sunnyvale CA, US
William G. Walker - Saratoga CA, US
Michael A. Zampaglione - San Jose CA, US

Assignee:

Virtual Silicon Technology, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 1, 716 4, 716 12, 716 15, 716 16, 716 17, 716 18

Abstract:

Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

US Patent:

6844770, Jan 18, 2005

Filed:

Apr 16, 2003

Appl. No.:

10/419050

Inventors:

Michael J. McManus - Liberty Township OH, US

Assignee:

Virtual Silicon Technology, Inc. - Sunnyvale CA

International Classification:

H03L 500

US Classification:

327333, 327108

Abstract:

Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.

US Patent:

7051308, May 23, 2006

Filed:

Jun 3, 2002

Appl. No.:

10/162120

Inventors:

Michael J. McManus - Liberty Township OH, US
Billie J. Rivera - San Jose CA, US
Richard Talburt - Sunnyvale CA, US
William G. Walker - Saratoga CA, US
Michael A. Zampaglione - San Jose CA, US

Assignee:

Virtual Silicon Technology, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 9, 716 10, 716 11, 716 12

Abstract:

Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

US Patent:

RE41982, Dec 7, 2010

Filed:

Jan 17, 2007

Appl. No.:

11/654492

Inventors:

Michael J. McManus - Liberty Township OH, US

International Classification:

H03L 5/00

US Classification:

327333, 327108

Abstract:

Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.

US Patent:

20130321054, Dec 5, 2013

Filed:

Aug 8, 2013

Appl. No.:

13/962191

Inventors:

Michael J. McManus - Liberty Township OH, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

H03K 5/06
G06F 17/50

US Classification:

327281, 716113

Abstract:

Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

US Patent:

20140082577, Mar 20, 2014

Filed:

Nov 25, 2013

Appl. No.:

14/088702

Inventors:

Michael J. McManus - Liberty Township OH, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716114

Abstract:

Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.