Michael G Mcneeley

US Patent:

20200409789, Dec 31, 2020

Filed:

Sep 10, 2020

Appl. No.:

17/017240

Inventors:

- Boise ID, US
Xiangang Luo - Fremont CA, US
Preston Allen Thomson - Boise ID, US
Michael G. McNeeley - Boise ID, US

International Classification:

G06F 11/10
G11C 29/52
G06F 3/06

Abstract:

A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

US Patent:

20200110661, Apr 9, 2020

Filed:

Oct 9, 2018

Appl. No.:

16/155573

Inventors:

- Boise ID, US
Xiangang Luo - Fremont CA, US
Preston Thomson - Boise ID, US
Michael G. McNeeley - Boise ID, US

International Classification:

G06F 11/10
G11C 29/52
G06F 3/06

Abstract:

A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

US Patent:

20190354421, Nov 21, 2019

Filed:

May 17, 2018

Appl. No.:

15/982653

Inventors:

- Boise ID, US
William C. Filipiak - Boise ID, US
Michael G. McNeeley - Boise ID, US
Kishore K. Muchherla - Fremont CA, US
Sampath K. Ratnam - Boise ID, US
Akira Goda - Boise ID, US
Todd A. Marquart - Boise ID, US

International Classification:

G06F 11/07
G11C 29/10

Abstract:

Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.