Michael W Morrison

US Patent:

6865086, Mar 8, 2005

Filed:

Jul 9, 2002

Appl. No.:

10/191139

Inventors:

Derek J. Gochnour - Boise ID, US
Walter L. Moden - Meridian ID, US
Michael W. Morrison - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05K005/02

US Classification:

361737, 235492

Abstract:

An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. The locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removable interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.

US Patent:

6970359, Nov 29, 2005

Filed:

Aug 3, 2004

Appl. No.:

10/911847

Inventors:

Derek J. Gochnour - Boise ID, US
Walter L. Moden - Meridian ID, US
Michael W. Morrison - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05K007/12

US Classification:

361737, 235492

Abstract:

An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. A locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removably interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.

US Patent:

7233064, Jun 19, 2007

Filed:

Mar 10, 2004

Appl. No.:

10/797647

Inventors:

Michael W. Morrison - Boise ID, US
Walter L. Moden - Meridian ID, US
Corey Jacobsen - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/04

US Classification:

257698, 257738, 257780

Abstract:

A semiconductor device assembly and method of making the devices are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

US Patent:

7323772, Jan 29, 2008

Filed:

Aug 28, 2002

Appl. No.:

10/233294

Inventors:

Michael W. Morrison - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/48

US Classification:

257692

Abstract:

Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The methods provide increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.

US Patent:

7378736, May 27, 2008

Filed:

Aug 13, 2004

Appl. No.:

10/917904

Inventors:

Michael W. Morrison - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/48

US Classification:

257738

Abstract:

Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The methods provide increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.

US Patent:

7501313, Mar 10, 2009

Filed:

Jul 10, 2006

Appl. No.:

11/483452

Inventors:

Michael W. Morrison - Boise ID, US
Walter L. Moden - Meridian ID, US
Corey Jacobsen - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/00

US Classification:

438118, 438122, 438123, 438124, 257698, 257738, 257780

Abstract:

A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

US Patent:

7663224, Feb 16, 2010

Filed:

Jul 10, 2006

Appl. No.:

11/483905

Inventors:

Michael W. Morrison - Boise ID, US
Walter L. Moden - Meridian ID, US
Corey Jacobsen - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/04

US Classification:

257698, 257738, 257780

Abstract:

A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of an electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

US Patent:

7709915, May 4, 2010

Filed:

May 7, 2008

Appl. No.:

12/116788

Inventors:

Michael W. Morrison - Boise ID, US

Assignee:

Aptina Imaging Corporation - Grand Cayman

International Classification:

H01L 21/00
H01L 31/00

US Classification:

257432, 257E21002, 438 65

Abstract:

Microelectronic devices having an EMI shield, systems including such microelectronic devices, and methods for manufacturing such microelectronic devices. One embodiment of a microelectronic device comprises an imaging system comprising a microelectronic die, an optics assembly, and an electromagnetic interference (EMI) shield. The microelectronic die includes an image sensor, processing components electrically coupled to the image sensor, a first interconnect electrically isolated from the processing components, and a second interconnect electrically coupled to the processing components. The optics assembly is aligned with the image sensor, and the electromagnetic interference (EMI) shield is between the optics assembly and the processing components. The EMI shield is electrically coupled to the first interconnect.