Michael Glenn Moser

US Patent:

61217999, Sep 19, 2000

Filed:

Apr 29, 1999

Appl. No.:

9/302016

Inventors:

Michael F. Moser - Beaverton OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H03K 522

US Classification:

327 58

Abstract:

An interleaved digital peak detector has multiple acquisition pipes with each pipe receiving a common input signal. Each acquisition pipe receives a common sample clock signal that is delayed through an analog delay circuit for selectively delaying the sample time of each analog-to-digital converter in the pipe. Each pipe has peak detector that receives the digitalized output from the analog-to-digital converter and accumulates maximum and minimum peak values. A programmable decimator receives the sample clock signal and a decimation value for establishing an acquisition clock by decimating the sample clock signal as a function of the decimation value to trigger a latch circuit for storing the accumulated maximum and minimum values from the peak detector. An acquisition memory stores the latched the maximum and minimum peak detector values over an acquisition interval and the maximum and minimum peak detector values from each of the acquisition pipes are compared over the acquisition interval under program control for generating a maximum and a minimum peak detector value over the acquisition interval for the acquisition pipes.

US Patent:

62791303, Aug 21, 2001

Filed:

Apr 30, 1999

Appl. No.:

9/303184

Inventors:

Michael F. Moser - Beaverton OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 1100

US Classification:

714724

Abstract:

A trigger delay compensation arrangement for use in a digital storage oscilloscope, includes a trigger circuit for receiving a TRIGGER OUT signal generated from a logic analyzer in response to a logic analyzer trigger event signal, for starting a post trigger counter. It also includes a data entry circuitry for entering data input by a user, the data being representative of a delay between a reception of the logic analyzer trigger event signal and the generation of the TRIGGER OUT signal by the logic analyzer. A post trigger counter stops an acquisition of signal data upon expiration of a count of the post trigger counter. A controller, coupled to the data entry circuitry and to the post trigger counter receives the delay representative data, and adjusts the count of the post trigger counter in a direction to compensate for the delay. The compensation delay allows display circuitry to display a portion of the acquisition that is centered about the logic analyzer trigger event, rather than the DSO trigger event.