Michael D Nelms

US Patent:

7444564, Oct 28, 2008

Filed:

Nov 19, 2003

Appl. No.:

10/707071

Inventors:

Darren L. Anand - Essex Junction VT, US
Kevin W. Gorman - Milton VT, US
Michael R. Nelms - Milton VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714723, 714733

Abstract:

A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.

US Patent:

7472325, Dec 30, 2008

Filed:

Apr 4, 2008

Appl. No.:

12/062599

Inventors:

Jeffrey H. Dreibelbis - Williston VT, US
Kevin W. Gorman - Milton VT, US
Michael R. Nelms - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G11C 29/00
G11C 7/00

US Classification:

714733, 714718, 365201

Abstract:

Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

US Patent:

20050172194, Aug 4, 2005

Filed:

Jan 29, 2004

Appl. No.:

10/707971

Inventors:

Jeffrey Dreibelbis - Williston VT, US
Kevin Gorman - Milton VT, US
Michael Nelms - Williston VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R031/28

US Classification:

714733000

Abstract:

Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.