Michael Glen Nielson

US Patent:

6438647, Aug 20, 2002

Filed:

Jun 23, 2000

Appl. No.:

09/602808

Inventors:

Michael E. Nielson - Broomfield CO
Thomas E. Richardson - Golden CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 118

US Classification:

711113, 713340

Abstract:

The present invention provides a method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system. Cooperation between a new replacement controller and a survivor controller is enabled so that write back cache operation can start immediately, and not be dependant on the battery condition in the replacement controller. Protection of the data through a single point of failure is maintained. When a controller fails, a replacement controller is installed and battery state information is exchanged. If any battery backup meets a predetermined threshold, all of the controllers run in the write back cache mode. However, if not one of the battery backups meets a predetermined threshold, all of the controllers run in the write through cache mode. Thus, the system does not need to wait for a replacement controllers battery backup to be reconditioned before the higher speed write back cache is used.

US Patent:

6625144, Sep 23, 2003

Filed:

Aug 18, 1999

Appl. No.:

09/376677

Inventors:

Mohamed H. El-Batal - Westminster CO
Michael Nielson - Broomfield CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1000

US Classification:

370364, 370465, 714 1

Abstract:

A circuit and special cable which allow a single DB9 connector to provide a standard RS-232 interface to a RAID controller in single RAID controller systems or to provide a controller-to-controller communication link for messaging, control and status signals when the special cable is used to interconnect two RAID controllers in a dual-active system.

US Patent:

6760807, Jul 6, 2004

Filed:

Nov 14, 2001

Appl. No.:

09/993235

Inventors:

William A. Brant - Boulder CO
William G. Deitz - Niwot CO
Michael E. Nielson - Broomfield CO
Joseph G. Skazinski - Berthoud CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711114, 711142, 711143, 711133, 711144

Abstract:

Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy. Reduces amount of host write data that has to be mirrored to alternate controller.

US Patent:

7197617, Mar 27, 2007

Filed:

May 29, 2003

Appl. No.:

10/447843

Inventors:

William Alexander Brant - Boulder CO, US
Michael Edward Nielson - Broomfield CO, US
Noel Simen Otterness - Lafayette CO, US
Thomas Elkins Richardson - Golden CO, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711170, 711112, 714758

Abstract:

A process, apparatus, and system stores data check information on an electronic storage medium that uses standard sector data field sizes. The check information may include a cyclic redundancy check (CRC), a logical block address (LBA), a longitudinal redundancy check (LRC), state information, a sequence number, or other information to identify data state, misplacement, or corruption. The check information, instead of being appended to the data within the data sector, may be stored in an independent check sector. The check information corresponding to multiple data sectors may also be aggregated and stored in a single check sector. The process or apparatus may be incorporated in a storage system controller, a RAID controller, a software SCSI stack in a computer, an operating system, a storage device driver, or another appropriate application that interfaces with standard and commodity storage system components.

US Patent:

20050071546, Mar 31, 2005

Filed:

Sep 25, 2003

Appl. No.:

10/671158

Inventors:

William Delaney - Wichita KS, US
Russell Henry - Wichita KS, US
Michael Nielson - Broomfield CO, US
Bret Weber - Wichita KS, US
Mohamad El-Batal - Westminster CO, US
Walter Hubis - Louisville CO, US

International Classification:

G06F012/00

US Classification:

711112000

Abstract:

Apparatus and methods are provided for improving scalability of a storage system. In one embodiment, a storage system comprising a stand-alone storage element that is reconfigurable to improve storage performance features of the storage system. The storage element comprises a plurality of disk drives, each configured for storing data. The storage element also comprises a storage controller communicatively adapted for coupling to a host computer system and configured for processing I/O requests received from the host computer system. The storage controller is also adaptable to interface with another storage controller added to the storage system. When adapted to communicate with the other storage controller, the storage controller of the stand-alone storage element can route the I/O requests to the other storage controller through a switching fabric.

US Patent:

56757263, Oct 7, 1997

Filed:

Nov 8, 1995

Appl. No.:

8/555331

Inventors:

Gerald Lee Hohenstein - Boulder CO
Michael E. Nielson - Broomfield CO
Tin S. Tang - Boulder CO
Richard D. Carmichael - Longmont CO
William A. Brant - Boulder CO

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1100

US Classification:

39518204

Abstract:

A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO.

US Patent:

58872701, Mar 23, 1999

Filed:

Sep 22, 1997

Appl. No.:

8/934909

Inventors:

William Alexander Brant - Boulder CO
Michael Edward Nielson - Broomfield CO
Gary Ward Howard - Boulder CO

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1200

US Classification:

711162

Abstract:

Data is recovered despite a single point of failure in a data exchanging system while accommodating scaleable data transfer rate performance. In the environment of at least two disk array controllers, a serial dumping scheme assists in recovery of data from a fast memory. It is imperative to avoid loss of write data from a host computer which is received and acknowledged but not yet stored in a disk medium. The configuration ensures that at least one of the controllers will handle the data so as to correct single failure point errors and properly store that data on one of the disks of an array. A fast memory providing a buffer between a remote host computer and arrays of data storage media is managed so that data received for writing is duplicated for reliability of storage while data for reading to the host computer is manipulated with an enhanced bandwidth of fast memory operation.

US Patent:

6010371, Jan 4, 2000

Filed:

Apr 24, 1997

Appl. No.:

8/842414

Inventors:

L. Scott Farley - Riverton UT
Dean T. Farrish - Salt Lake City UT
Russell D. Heyborne - West Valley UT
Kevin H. Johnson - West Jordan UT
Michael S. Nielson - Sandy UT
Steven B. Shannon - Sandy UT

Assignee:

Abbott Laboratories - Abbott Park IL

International Classification:

H01R 2302

US Classification:

439676

Abstract:

A connector is provided for terminating a multi-conductor, flexible cable of the flat ribbon type which has a plurality of conductors in side-by-side parallel, spaced relationship within a web of encapsulating insulation from which projects a pre-stripped, bare, distal end portion of each conductor. The connector includes a housing defining a passage extending from an open first end to an open second end. The housing includes divider walls defining a plurality of slots each opening outwardly and each communicating with the passage at the second end. The housing has a support wall defining a bottom in each slot. An insulated length of cable can extend through the open first end of the housing passage toward the open second end where each bare, distal end portion of the conductor can be exposed and bent in one of the slots around the support wall adjacent a bottom of a slot.