Michael W Osborn

US Patent:

6448815, Sep 10, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/699729

Inventors:

Gerald Talbot - Concord MA
Michael J. Osborn - Wellesley MA
Mark D. Hummel - Franklin MA

Assignee:

API NetWorks, Inc. - Concord MA

International Classification:

H03K 19094

US Classification:

326 86, 326 30, 326 34

Abstract:

A low-voltage transmitter and receiver adapted for differential signaling via transmission lines between integrated circuits enables operation at very-high data exchange rates. Such data transmission is achieved in a manner that minimizes reflected energy and minimizes crosstalk between signals propagating over neighboring transmission lines. In achieving optimal transmission characteristics, a bridge circuit is employed to drive the signal. The bridge circuit is connected in series between a pull-up and pull-down resistance, their respective resistance values being programmable to maintain optimal communication rates and quality. The pull-up and pull-down resistors preferably comprise a bank of transistors having source-to-drain resistance values that are binary multiples of each other. The transistors are preferably coupled in parallel with each other and in parallel with a resistor, such that the transistors can be selectively activated by a binary voltage control data word. By activating different transistors in the network, different overall resistance values can be achieved.

US Patent:

7984351, Jul 19, 2011

Filed:

Apr 10, 2008

Appl. No.:

12/100453

Inventors:

Jonathan M. Owen - Northboro MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 11/00
G06F 1/00
G01R 31/28

US Classification:

714731, 714 30, 714744, 713500

Abstract:

A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

US Patent:

8001409, Aug 16, 2011

Filed:

May 18, 2007

Appl. No.:

11/750443

Inventors:

Michael J. Osborn - Hollis NH, US
Mark D. Hummel - Franklin MA, US
Denis Rystsov - Arlington MA, US

International Classification:

G06F 1/12

US Classification:

713400, 345558

Abstract:

A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.

US Patent:

8583971, Nov 12, 2013

Filed:

Dec 23, 2010

Appl. No.:

12/977338

Inventors:

Sajosh Janarthanam - Austin TX, US
Jonathan Owen - Northborough MA, US
Michael Osborn - Hollis NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 29/00

US Classification:

714719, 714801, 714805

Abstract:

A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

US Patent:

8584067, Nov 12, 2013

Filed:

Nov 2, 2010

Appl. No.:

12/938125

Inventors:

Michael J. Osborn - Hollis NH, US
Michael J. Tresidder - Newmarket, CA
Aaron J. Grenat - Austin TX, US
Joseph Kidd - Hudson MA, US
Priyank Parakh - Arlington MA, US
Steven J. Kommrusch - Fort Collins CO, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716113, 716114, 716124, 716135, 716136, 703 13, 703 19

Abstract:

Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

US Patent:

20120266179, Oct 18, 2012

Filed:

Apr 14, 2011

Appl. No.:

13/087206

Inventors:

Michael J. Osborn - Hollis NH, US
Sebastien J. Nussbaum - Lexington MA, US

International Classification:

G06F 9/46

US Classification:

718105

Abstract:

A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of logical cores to the plurality of physical cores. The processor further includes an assignment unit configured to remap the logical cores to the plurality of physical cores subsequent to a boot process of the processor. In some embodiments, the assignment unit is configured to remap the logical cores in response to receiving an indication that one or more of the plurality of physical cores have entered an idle state. The processor may be configured to load a first of the plurality of physical cores with an execution state of a second of the plurality of physical cores upon the first physical core exiting an idle state.

US Patent:

20130297950, Nov 7, 2013

Filed:

May 7, 2012

Appl. No.:

13/465680

Inventors:

Michael J. Osborn - Hollis NH, US
Sebastien Nussbaum - Lexington MA, US
John P. Petry - San Diego CA, US
Umair B. Cheema - Richmond Hill, CA

Assignee:

Advanced Micro Devices, Inc., - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

A method and system for determining voltage supplied to a processor from a voltage regulator when the voltage cannot be directly measured.

US Patent:

20130304841, Nov 14, 2013

Filed:

May 14, 2012

Appl. No.:

13/470847

Inventors:

Mark Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 15/167

US Classification:

709212

Abstract:

Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.