Michael J Osborn

US Patent:

6448815, Sep 10, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/699729

Inventors:

Gerald Talbot - Concord MA
Michael J. Osborn - Wellesley MA
Mark D. Hummel - Franklin MA

Assignee:

API NetWorks, Inc. - Concord MA

International Classification:

H03K 19094

US Classification:

326 86, 326 30, 326 34

Abstract:

A low-voltage transmitter and receiver adapted for differential signaling via transmission lines between integrated circuits enables operation at very-high data exchange rates. Such data transmission is achieved in a manner that minimizes reflected energy and minimizes crosstalk between signals propagating over neighboring transmission lines. In achieving optimal transmission characteristics, a bridge circuit is employed to drive the signal. The bridge circuit is connected in series between a pull-up and pull-down resistance, their respective resistance values being programmable to maintain optimal communication rates and quality. The pull-up and pull-down resistors preferably comprise a bank of transistors having source-to-drain resistance values that are binary multiples of each other. The transistors are preferably coupled in parallel with each other and in parallel with a resistor, such that the transistors can be selectively activated by a binary voltage control data word. By activating different transistors in the network, different overall resistance values can be achieved.

US Patent:

7984351, Jul 19, 2011

Filed:

Apr 10, 2008

Appl. No.:

12/100453

Inventors:

Jonathan M. Owen - Northboro MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 11/00
G06F 1/00
G01R 31/28

US Classification:

714731, 714 30, 714744, 713500

Abstract:

A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

US Patent:

20130304841, Nov 14, 2013

Filed:

May 14, 2012

Appl. No.:

13/470847

Inventors:

Mark Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 15/167

US Classification:

709212

Abstract:

Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.

US Patent:

20130339466, Dec 19, 2013

Filed:

Jun 19, 2012

Appl. No.:

13/526973

Inventors:

David E. Mayhew - Northborough MA, US
Mark Hummel - Franklin MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 15/167

US Classification:

709212

Abstract:

Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.

US Patent:

20130346531, Dec 26, 2013

Filed:

Jun 25, 2012

Appl. No.:

13/531890

Inventors:

Mark Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US
Michael J. Osborn - Hollis NH, US
Anton Chernoff - Littleton MA, US
Venkata S. Krishnan - Ashland MA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

H04L 12/56
H04L 12/28
G06F 15/167
H04L 12/66

US Classification:

709212, 370401, 370352, 370254, 370255

Abstract:

Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

US Patent:

20140059160, Feb 27, 2014

Filed:

Aug 21, 2012

Appl. No.:

13/590700

Inventors:

Anton Chernoff - Littleton MA, US
Venkata S. Krishnan - Ashland MA, US
Mark Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 15/173
G06F 15/16

US Classification:

709217, 709223, 709224

Abstract:

Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.

US Patent:

20140068205, Mar 6, 2014

Filed:

Sep 4, 2012

Appl. No.:

13/602725

Inventors:

David E. Mayhew - Northborough MA, US
Mark Hummel - Franklin MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 12/12

US Classification:

711159

Abstract:

Described are systems and methods for transmitting data at an aggregation device. The aggregation device includes a record queue and an output bypass queue. The data is received from an electronic device. A record is generated of the received data. The record is placed in the record queue. A determination is made that the record in the record queue is blocked. The blocked record is transferred from the record queue to the output bypass queue.

US Patent:

20160004445, Jan 7, 2016

Filed:

Sep 14, 2015

Appl. No.:

14/852812

Inventors:

David E. Mayhew - Northborough MA, US
Mark D. Hummel - Franklin MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 3/06

Abstract:

Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.