Michael L Osborn

US Patent:

8001409, Aug 16, 2011

Filed:

May 18, 2007

Appl. No.:

11/750443

Inventors:

Michael J. Osborn - Hollis NH, US
Mark D. Hummel - Franklin MA, US
Denis Rystsov - Arlington MA, US

International Classification:

G06F 1/12

US Classification:

713400, 345558

Abstract:

A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.

US Patent:

8584067, Nov 12, 2013

Filed:

Nov 2, 2010

Appl. No.:

12/938125

Inventors:

Michael J. Osborn - Hollis NH, US
Michael J. Tresidder - Newmarket, CA
Aaron J. Grenat - Austin TX, US
Joseph Kidd - Hudson MA, US
Priyank Parakh - Arlington MA, US
Steven J. Kommrusch - Fort Collins CO, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716113, 716114, 716124, 716135, 716136, 703 13, 703 19

Abstract:

Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

US Patent:

20120266179, Oct 18, 2012

Filed:

Apr 14, 2011

Appl. No.:

13/087206

Inventors:

Michael J. Osborn - Hollis NH, US
Sebastien J. Nussbaum - Lexington MA, US

International Classification:

G06F 9/46

US Classification:

718105

Abstract:

A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of logical cores to the plurality of physical cores. The processor further includes an assignment unit configured to remap the logical cores to the plurality of physical cores subsequent to a boot process of the processor. In some embodiments, the assignment unit is configured to remap the logical cores in response to receiving an indication that one or more of the plurality of physical cores have entered an idle state. The processor may be configured to load a first of the plurality of physical cores with an execution state of a second of the plurality of physical cores upon the first physical core exiting an idle state.

US Patent:

20130297950, Nov 7, 2013

Filed:

May 7, 2012

Appl. No.:

13/465680

Inventors:

Michael J. Osborn - Hollis NH, US
Sebastien Nussbaum - Lexington MA, US
John P. Petry - San Diego CA, US
Umair B. Cheema - Richmond Hill, CA

Assignee:

Advanced Micro Devices, Inc., - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

A method and system for determining voltage supplied to a processor from a voltage regulator when the voltage cannot be directly measured.

US Patent:

20130318372, Nov 28, 2013

Filed:

May 24, 2012

Appl. No.:

13/479597

Inventors:

Michael J. Osborn - Hollis NH, US
Sebastien Nussbaum - Lexington MA, US
John P. Petry - San Diego CA, US
Umair B. Cheema - Richmond Hill, CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713320, 713300

Abstract:

A method of controlling voltage in a circuit is provided. Within the circuit, a block of an electrical component provides an indication that it desires to switch states (such as from off to on, on to off, or from one speed to another). The change in states requires a different current draw by the electrical component block. The indication is received by an electrical component that controls the voltage of the circuit. The electrical component that controls the voltage then issues a signal granting permission for the electrical component block to switch states. This permission signal is received by the electrical component and the electrical component block changes state.

US Patent:

20140068139, Mar 6, 2014

Filed:

Aug 29, 2012

Appl. No.:

13/597730

Inventors:

Michael J. Osborn - Hollis NH, US
Mark D. Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 12/02
G06F 12/06

US Classification:

711101, 711173, 711E12084, 711E12007

Abstract:

A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.

US Patent:

20140068220, Mar 6, 2014

Filed:

Sep 6, 2012

Appl. No.:

13/605150

Inventors:

Michael J. Osborn - Hollis NH, US
David E. Mayhew - Northborough MA, US
Mark D. Hummel - Franklin MA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 12/02

US Classification:

711170, 711E12002

Abstract:

A hardware based memory allocation system in a computer includes: a memory module formatted with memory blocks; an input controller, in communications with the memory module and receiving a transfer request from a requestor, for transferring data from a source to the memory module; an output controller, in communications with the memory module and the input controller, for transferring data from the memory module to a destination; and a block allocator, in communications the input controller and the output controller, for maintaining a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module.

US Patent:

20140068373, Mar 6, 2014

Filed:

Sep 6, 2012

Appl. No.:

13/605218

Inventors:

Michael J. Osborn - Hollis NH, US
Mark D. Hummel - Franklin MA, US
David E. Mayhew - Northborough MA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

H03M 13/29
G06F 11/10

US Classification:

714755, 714E11034

Abstract:

A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.