Michael J Osborn

US Patent:

6448815, Sep 10, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/699729

Inventors:

Gerald Talbot - Concord MA
Michael J. Osborn - Wellesley MA
Mark D. Hummel - Franklin MA

Assignee:

API NetWorks, Inc. - Concord MA

International Classification:

H03K 19094

US Classification:

326 86, 326 30, 326 34

Abstract:

A low-voltage transmitter and receiver adapted for differential signaling via transmission lines between integrated circuits enables operation at very-high data exchange rates. Such data transmission is achieved in a manner that minimizes reflected energy and minimizes crosstalk between signals propagating over neighboring transmission lines. In achieving optimal transmission characteristics, a bridge circuit is employed to drive the signal. The bridge circuit is connected in series between a pull-up and pull-down resistance, their respective resistance values being programmable to maintain optimal communication rates and quality. The pull-up and pull-down resistors preferably comprise a bank of transistors having source-to-drain resistance values that are binary multiples of each other. The transistors are preferably coupled in parallel with each other and in parallel with a resistor, such that the transistors can be selectively activated by a binary voltage control data word. By activating different transistors in the network, different overall resistance values can be achieved.

US Patent:

6990383, Jan 24, 2006

Filed:

Jan 29, 2004

Appl. No.:

10/767799

Inventors:

Vern Richard Hoppes - Waterloo IA, US
Larry Linn Kriener - Waterloo IA, US
Matthew Jon Pipho - Waterloo IA, US
Joshua Mark Edgin - Cedar Falls IA, US
James Anthony Mitchell - Waterloo IA, US
Ibrahim Hussein Shehata - Cedar Falls IA, US
Anthony Nate Rath - Cedar Falls IA, US
Robert Joseph Mills - Cedar Falls IA, US
Michael Eugene Osborn - Sumner IA, US
Mark Douglas Smith - Cedar Falls IA, US
Terry John Phillips - Waterloo IA, US
Kevin Dean Bortolazzo - Cedar Falls IA, US
Dave Anthony Sink - Waterloo IA, US
Joel Floyd Myers - Hudson IA, US
Kenneth John Kresser - Evansdale IA, US
Gary Lee Miner - Cedar Falls IA, US
Lesley Ann McNaught - Waterloo IA, US

Assignee:

Deere & Company - Moline IL

International Classification:

G06F 19/00

US Classification:

700109, 700 95, 702 84

Abstract:

Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor. Parts bins and assembly points may be indicated by visual or other means to indicate parts and tools to be used and assembly points.

US Patent:

7010375, Mar 7, 2006

Filed:

Jun 2, 2005

Appl. No.:

11/143211

Inventors:

Vern Richard Hoppes - Waterloo IA, US
Larry Linn Kriener - Waterloo IA, US
Matthew Jon Pipho - Waterloo IA, US
Joshua Mark Edgin - Cedar Falls IA, US
James Anthony Mitchell - Waterloo IA, US
Ibrahim Hussein Shehata - Cedar Falls IA, US
Anthony Nate Rath - Cedar Falls IA, US
Robert Joseph Mills - Cedar Falls IA, US
Michael Eugene Osborn - Sumner IA, US
Mark Douglas Smith - Cedar Falls IA, US
Terry John Phillips - Waterloo IA, US
Kevin Dean Bortolazzo - Cedar Falls IA, US
Dave Anthony Sink - Waterloo IA, US
Joel Floyd Myers - Hudson IA, US
Kenneth John Kresser - Evansdale IA, US
Gary Lee Miner - Cedar Falls IA, US
Lesley Ann McNaught - Waterloo IA, US

Assignee:

Deere & Company - Moline IL

International Classification:

G06F 19/00

US Classification:

700109, 700 95, 702 84

Abstract:

Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor. Parts bins and assembly points may be indicated by visual or other means to indicate parts and tools to be used and assembly points.

US Patent:

7013193, Mar 14, 2006

Filed:

Jun 2, 2005

Appl. No.:

11/143062

Inventors:

Vern Richard Hoppes - Waterloo IA, US
Larry Linn Kriener - Waterloo IA, US
Matthew Jon Pipho - Waterloo IA, US
Joshua Mark Edgin - Cedar Falls IA, US
James Anthony Mitchell - Waterloo IA, US
Ibrahim Hussein Shehata - Cedar Falls IA, US
Anthony Nate Rath - Cedar Falls IA, US
Robert Joseph Mills - Cedar Falls IA, US
Michael Eugene Osborn - Sumner IA, US
Mark Douglas Smith - Cedar Falls IA, US
Terry John Phillips - Waterloo IA, US
Kevin Dean Bortolazzo - Cedar Falls IA, US
Dave Anthony Sink - Waterloo IA, US
Joel Floyd Myers - Hudson IA, US
Kenneth John Kresser - Evansdale IA, US
Gary Lee Miner - Cedar Falls IA, US
Lesley Ann McNaught - Waterloo IA, US

Assignee:

Deere & Company - Moline IL

International Classification:

G06F 19/00

US Classification:

700109, 700 95, 700103, 702 81

Abstract:

Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor. Parts bins and assembly points may be indicated by visual or other means to indicate parts and tools to be used and assembly points.

US Patent:

7013194, Mar 14, 2006

Filed:

Jun 2, 2005

Appl. No.:

11/143066

Inventors:

Vern Richard Hoppes - Waterloo IA, US
Larry Linn Kriener - Waterloo IA, US
Matthew Jon Pipho - Waterloo IA, US
Joshua Mark Edgin - Cedar Falls IA, US
James Anthony Mitchell - Waterloo IA, US
Ibrahim Hussein Shehata - Cedar Falls IA, US
Anthony Nate Rath - Cedar Falls IA, US
Robert Joseph Mills - Milan IL, US
Michael Eugene Osborn - Sumner IA, US
Mark Douglas Smith - Cedar Falls IA, US
Terry John Phillips - Waterloo IA, US
Kevin Dean Bortolazzo - Cedar Falls IA, US
Dave Anthony Sink - Waterloo IA, US
Joel Floyd Myers - Hudson IA, US
Kenneth John Kresser - Evansdale IA, US
Gary Lee Miner - Cedar Falls IA, US
Lesley Ann McNaught - Waterloo IA, US

Assignee:

Deere & Company - Moline IL

International Classification:

G06F 19/00

US Classification:

700109, 700 95, 702 84

Abstract:

Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor. Parts bins and assembly points may be indicated by visual or other means to indicate parts and tools to be used and assembly points.

US Patent:

7027886, Apr 11, 2006

Filed:

Jun 2, 2005

Appl. No.:

11/143079

Inventors:

Vern Richard Hoppes - Waterloo IA, US
Larry Linn Kriener - Waterloo IA, US
Matthew Jon Pipho - Waterloo IA, US
Joshua Mark Edgin - Cedar Falls IA, US
James Anthony Mitchell - Waterloo IA, US
Ibrahim Hussein Shehata - Cedar Falls IA, US
Anthony Nate Rath - Cedar Falls IA, US
Robert Joseph Mills - Cedar Falls IA, US
Michael Eugene Osborn - Sumner IA, US
Mark Douglas Smith - Cedar Falls IA, US
Terry John Phillips - Waterloo IA, US
Kevin Dean Bortolazzo - Cedar Falls IA, US
Dave Anthony Sink - Waterloo IA, US
Joel Floyd Myers - Hudson IA, US
Kenneth John Kresser - Evansdale IA, US
Gary Lee Miner - Cedar Falls IA, US
Lesley Ann McNaught - Waterloo IA, US

Assignee:

Deere & Company - Moline IL

International Classification:

G06F 19/00

US Classification:

700108, 700 28, 700 95, 702 84

Abstract:

Interfaces are provided which integrate mistake-proofing concepts in a way easily understandable by the operator and easily configured by a manufacturing engineer. As mistake-proofing concepts are developed tables are populated and associated with specific assembly processes. Sensors are employed to monitor parts selection and tool usage. Sensors used for tool use and parts selection, error messages and actions to be performed or monitored are all defined and related in the tables and in turn to specific assembly orders. The tables are also populated with logic pointers, which are referenced by a Process Logic Control (PLC) unit that has been programmed to recall and carry out infinitely variable monitoring or control of the assembly process. For example when a particular order has been identified to the PLC by way of a scanned barcode or other means, a bill of material and assembly sequence is provided to the operator by appropriate means such as a CRT monitor. Parts bins and assembly points may be indicated by visual or other means to indicate parts and tools to be used and assembly points.

US Patent:

7984351, Jul 19, 2011

Filed:

Apr 10, 2008

Appl. No.:

12/100453

Inventors:

Jonathan M. Owen - Northboro MA, US
Michael J. Osborn - Hollis NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 11/00
G06F 1/00
G01R 31/28

US Classification:

714731, 714 30, 714744, 713500

Abstract:

A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

US Patent:

8001409, Aug 16, 2011

Filed:

May 18, 2007

Appl. No.:

11/750443

Inventors:

Michael J. Osborn - Hollis NH, US
Mark D. Hummel - Franklin MA, US
Denis Rystsov - Arlington MA, US

International Classification:

G06F 1/12

US Classification:

713400, 345558

Abstract:

A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.