Michael L Ott

US Patent:

6384279, May 7, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943536

Inventors:

James E. Deline - Livermore CA
Michael M. Ott - Oakland CA

Assignee:

The Clorox Company - Oakland CA

International Classification:

C07C23102

US Classification:

564142, 564143, 564155, 564159, 564160, 562408, 562409, 562418, 562538, 562565

Abstract:

A new composition of matter for a diamidodiol and a method for preparing the diamidodiol. The exemplary diamidodiol has the formula C H N O and is prepared by reacting a first quantity of 2-amino-2-methyl-1-propanol with a second quantity of a di-substituted malonyl dichloride (i. e. , diethylmalonyl dichloride), preferably in ethyl acetate as solvent. A tetraamido macrocycle is prepared from the diamidodiol in two steps by oxidizing the diamidodiol to form a diacid followed by coupling using a known procedure of the diacid with an aryl diamine (e. g. , 1,2-diaminobenzene) to yield the tetraamido macrocycle.

US Patent:

6477552, Nov 5, 2002

Filed:

Nov 18, 1999

Appl. No.:

09/443225

Inventors:

Michael L. Ott - Walnut Creek CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

708211

Abstract:

A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal. Further, adders generate a no-carryout signal by offsetting the priority encoded signal with a second portion of the offset, and generate a carryout signal by offsetting the priority encoded signal with the second portion of the offset and adding one. A mux then selects one of the no-carryout and carryout signals as a second portion of the consecutive clear bits count in accordance with the carryout selector signal.

US Patent:

6598066, Jul 22, 2003

Filed:

May 23, 2000

Appl. No.:

09/577211

Inventors:

Michael L. Ott - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 750

US Classification:

708710

Abstract:

A carry-out bit generator determines if a bit pattern from two positive numbers matches one of the patterns for which a carry-out bit would be generated in addition. These patterns include a T G pattern and a T pattern (with a carry-in). Superscript n represents a number between zero and m-1, superscript m represents the number of registers, T represents a 0/1 or 1/0 pair and G represents a 1/1 pair.

US Patent:

6654775, Nov 25, 2003

Filed:

Feb 23, 2000

Appl. No.:

09/511218

Inventors:

Michael L. Ott - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

708211

Abstract:

An optimized system and method for a parallel leading zero anticipation which ascertains âend of runâ patterns in parallel. A string representing the operands of the floating-point addition is divided into nibbles of predetermined bit length (normally 4 bits). Each nibble is analyzed for the end of run patterns and the results from this analysis determine whether a run of leading zeros or ones has ended within the nibble, and if there has been an end of run, the location (bit) of the end of run. The highest order nibble that has an end of run provides the higher order bits in the LZA (leading zero anticipator output) value, while the lower two bits of the LZA value are correlated from the location end of run within the nibble, as previously determined.

US Patent:

6742105, May 25, 2004

Filed:

Dec 22, 2000

Appl. No.:

09/748052

Inventors:

Michael L. Ott - Pleasanton CA

Assignee:

Silicon Access Networks - San Jose CA

International Classification:

G06F 1200

US Classification:

711220, 711 5, 711173, 711216

Abstract:

A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.

US Patent:

6769005, Jul 27, 2004

Filed:

Feb 13, 2001

Appl. No.:

09/782637

Inventors:

Michael Ott - Pleasanton CA

Assignee:

Silicon Access Networks - San Jose CA

International Classification:

G06F 1500

US Classification:

708207

Abstract:

A method and apparatus for resolving priority among a plurality of data values. The priority resolution method of the invention analyzes the data values one bit at a time, starting from the most significant bit. In one embodiment, at an initial analysis step, the method determines whether the most significant bits of the data values are asserted. If at least one of the most significant bits is asserted, the data values that have unasserted most significant bits are eliminated from consideration. If none of the most significant bits is asserted, none of the data values will be eliminated at the initial step. The same analysis steps are repeated for each successive bit until only the largest data values remain. The priority resolution method of the present invention may be used to determine the smallest data value. In that embodiment, the data values are first bit-wise inverted.

US Patent:

6774786, Aug 10, 2004

Filed:

Nov 7, 2000

Appl. No.:

09/707580

Inventors:

Robert B. Havekost - Austin TX
Trevor D. Schleiss - Austin TX
Michael G. Ott - Austin TX
Cindy Scott - Georgetown TX
J. Clint Fletcher - Pflugerville TX

Assignee:

Fisher-Rosemount Systems, Inc. - Austin TX

International Classification:

G08B 2300

US Classification:

340517, 340500, 340525, 340506, 340521, 700 17, 700 83, 702183, 702188

Abstract:

An alarm display and interface tool for use in a process control system receives and displays different categories of alarms, including for example, device alarms and hardware alarms as well as traditional process alarms, on a single display to enable an operator or other user to view and have access to these different categories of alarms. The display and interface tool may be used to filter the alarms that are displayed according to any number of categories, including the category of the alarm, the priority of the alarm, the status of the alarm, etc. so as to alternatively segregate or combine the tasks typically associated with operator, maintenance and engineer personnel. The tool may also be used to access each of the displayed alarms to obtain more information about any individual alarm.

US Patent:

6868538, Mar 15, 2005

Filed:

May 2, 2000

Appl. No.:

09/563212

Inventors:

Mark J. Nixon - Round Rock TX, US
Dennis L. Stevenson - Round Rock TX, US
Michael G. Ott - Austin TX, US
Stephen G. Hammack - Austin TX, US

Assignee:

Fisher-Rosemount Systems, Inc. - Austin TX

International Classification:

G06F009/44
G05B015/00

US Classification:

717100, 700 83

Abstract:

An apparatus having a programmable processor and a memory for performing a plurality of user-selectable control functions includes a database for storing a plurality of items associated with each of the control functions. The items include, for each function, at least one procedure for performing an action associated with the control function and a specification of at least one state associated with the control function. The apparatus further includes software routines stored on the memory and adapted to be executed by the processor that facilitate selection of a procedure in the database, that access the database and cause performance of the selected procedure to achieve the state specified therein, and that monitor at least one resource associated with the action of the procedure and, based thereon, determine whether the specified state has been achieved.