Michael C Parris

US Patent:

20130107630, May 2, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284783

Inventors:

David Edward Fisch - Pleasanton CA, US
Michael Curtis Parris - San Jose CA, US

Assignee:

INVENSAS CORPORATION - San Jose CA

International Classification:

G11C 16/04
H01L 29/788
H01L 21/336
H01L 29/94

US Classification:

36518518, 257298, 257315, 438257, 257E293, 257E29345, 257E21422

Abstract:

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

US Patent:

20130107635, May 2, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284795

Inventors:

David Edward Fisch - Pleasanton CA, US
William C. Plants - Campbell CA, US
Michael Curtis Parris - San Jose CA, US

Assignee:

INVENSAS CORPORATION - San Jose CA

International Classification:

G11C 16/10
G11C 16/04

US Classification:

36518533, 36518518

Abstract:

An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.