Michael S Parris

Address:

175 W Saint James St UNIT 1303, San Jose, CA 95110

VIN:

1G2AL15F277252675

Make:

PONTIAC

Model:

G5

Year:

2007

US Patent:

20130027056, Jan 31, 2013

Filed:

Jul 29, 2011

Appl. No.:

13/194669

Inventors:

Michael Curtis Parris - San Jose CA, US

Assignee:

TESSERA INC. - San Jose CA

International Classification:

G01R 31/07

US Classification:

324550

Abstract:

System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.

US Patent:

20130027899, Jan 31, 2013

Filed:

Jul 29, 2011

Appl. No.:

13/194754

Inventors:

Michael Curtis Parris - San Jose CA, US

Assignee:

TESSERA, INC. - San Jose CA

International Classification:

H05K 7/00
H01L 21/50

US Classification:

361820, 438107, 257E21499

Abstract:

System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply.

US Patent:

20130107630, May 2, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284783

Inventors:

David Edward Fisch - Pleasanton CA, US
Michael Curtis Parris - San Jose CA, US

Assignee:

INVENSAS CORPORATION - San Jose CA

International Classification:

G11C 16/04
H01L 29/788
H01L 21/336
H01L 29/94

US Classification:

36518518, 257298, 257315, 438257, 257E293, 257E29345, 257E21422

Abstract:

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

US Patent:

20130107635, May 2, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284795

Inventors:

David Edward Fisch - Pleasanton CA, US
William C. Plants - Campbell CA, US
Michael Curtis Parris - San Jose CA, US

Assignee:

INVENSAS CORPORATION - San Jose CA

International Classification:

G11C 16/10
G11C 16/04

US Classification:

36518533, 36518518

Abstract:

An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.

US Patent:

20140253145, Sep 11, 2014

Filed:

May 23, 2014

Appl. No.:

14/286159

Inventors:

- SAN JOSE CA, US
Michael Curtis Parris - San Jose CA, US

Assignee:

TESSERA, INC. - SAN JOSE CA

International Classification:

G01R 31/07

US Classification:

324550

Abstract:

System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.