Michael D Parris

US Patent:

6414897, Jul 2, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/651939

Inventors:

Kim Carver Hardee - Colorado Springs CO
Michael Parris - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G11C 800

US Classification:

36523006, 365190

Abstract:

A local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal to couple complimentary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.

US Patent:

6501817, Dec 31, 2002

Filed:

Nov 13, 2001

Appl. No.:

10/010336

Inventors:

Michael Parris - Colorado Springs CO
Kim Hardee - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G06M 300

US Classification:

377 68, 377 26, 377 54, 377 75, 365200, 365201, 714718, 714805

Abstract:

An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or âpassâ gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (V ) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of V. The V voltage and circuit ground (âGNDâ) are then utilized as the logic âhighâ and âlowâ signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (âDCâ) level after device power-up.

US Patent:

6512394, Jan 28, 2003

Filed:

Mar 14, 2002

Appl. No.:

10/098872

Inventors:

Michael C. Parris - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

H03K 1716

US Classification:

326 34, 326 33, 327530, 365226

Abstract:

A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.

US Patent:

6515926, Feb 4, 2003

Filed:

Jan 4, 2002

Appl. No.:

10/038932

Inventors:

Michael C. Parris - Colorado Springs CO
Kim C. Hardee - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G11C 700

US Classification:

365205, 365207, 36518905

Abstract:

A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e. g. latch P-channel âLPâ) electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e. g. latch N-channel âLNâ) electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, âwriteâ recovery time can be significantly improved over that of conventional layouts and designs.

US Patent:

6549470, Apr 15, 2003

Filed:

Aug 17, 2001

Appl. No.:

09/932331

Inventors:

Kim Carver Hardee - Colorado Springs CO
Michael Curtis Parris - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G11C 1604

US Classification:

36518905, 36523006, 36523008

Abstract:

A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.

US Patent:

6570799, May 27, 2003

Filed:

Mar 14, 2002

Appl. No.:

10/099333

Inventors:

Michael C. Parris - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G11C 700

US Classification:

365203, 365205, 36518905

Abstract:

A pre-charge and reference voltage technique operates on a DRAM memory array in which two additional rows of reference cells are added to the array. When the array starts the pre-charge cycle, the regular word line and latch P-channel bar signals both turn off and the complementary bit line pair is shorted together. These two lines charge share to create a half way voltage level (VCC/2) that is restored into the reference cell. After this voltage is restored into the reference cell, the bit lines are fully pre-charged to ground.

US Patent:

6597201, Jul 22, 2003

Filed:

Aug 29, 2000

Appl. No.:

09/650494

Inventors:

Michael C. Parris - Colorado Springs CO
Kim Carver Hardee - Colorado Springs CO

Assignee:

Mosel Vitelic, Inc. - Wsinchu

International Classification:

H03K 190185

US Classification:

326 93, 326 95, 326108, 326105, 327208, 365203, 36523006

Abstract:

A predecoder circuit for use in association with a memory circuit is shown to have a dynamic NAND gate formed by series-coupled transistors controlled by a bank active select signal and a row address selection signal. The predecoder circuit also includes a precharge circuit coupled to the dynamic NAND gate and controlled by a precharge signal. The predecoder circuit further includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and an output terminal selectively electrically connectable to at least one row decoder circuit for the memory circuit. The predecoder circuit finally includes a second inverter arranged in feedback with the first inverter to form a latch.

US Patent:

6608797, Aug 19, 2003

Filed:

Apr 18, 2002

Appl. No.:

10/125756

Inventors:

Michael C. Parris - Colorado Springs CO
Kim C. Hardee - Colorado Springs CO

Assignee:

United Memories, Inc. - Colorado Springs CO
Sony Corporation - Tokyo

International Classification:

G11C 800

US Classification:

365233, 365194, 36523006

Abstract:

An automatic delay technique for early âreadâ and âwriteâ memory access operations in synchronous dynamic random access memory (âSDRAMâ) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (âYiâ) and data signals such that the column address strobe (â/CASâ) signal is allowed to go âactiveâ in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (âreadâ or âwriteâ) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.