Michael Shawn Patrick

Address:

10102 Storm Mdw Dr, Houston, TX 77064

VIN:

1HD1HHZ137K805026

Make:

Cadillac

Model:

Escalade ESV AWD 4dr

Year:

2007

US Patent:

47978082, Jan 10, 1989

Filed:

Jun 22, 1981

Appl. No.:

6/276421

Inventors:

Jeffrey D. Bellay - Houston TX
Kevin C. McDonough - Houston TX
Michael W. Patrick - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 900

US Classification:

364200

Abstract:

A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all macrocode bits is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to address all bytes of macrocode and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.

US Patent:

45802165, Apr 1, 1986

Filed:

Jun 22, 1981

Appl. No.:

6/276412

Inventors:

Jeffrey D. Bellay - Houston TX
Kevin C. McDonough - Houston TX
Michael W. Patrick - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 922

US Classification:

364200

Abstract:

A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. In the normal single-chip operation mode, a macrocode word is fethched from on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. In another mode, such as used for self-test employing a check-code, the device loads macrocode from external into on-chip RAM then executes from RAM to perform the desired routine, switching modes of operation.

US Patent:

46462325, Feb 24, 1987

Filed:

Jan 3, 1984

Appl. No.:

6/567596

Inventors:

Ki S. Chang - Houston TX
Michael W. Patrick - Houston TX
Stephen P. Sacarisen - Houston TX
Mark A. Stambaugh - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

US Patent:

47775912, Oct 11, 1988

Filed:

Oct 23, 1986

Appl. No.:

6/922362

Inventors:

Ki S. Chang - Houston TX
Michael W. Patrick - Houston TX
Stephen P. Sacarisen - Houston TX
Mark A. Stambaugh - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1318

US Classification:

364200

Abstract:

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus.

US Patent:

45424535, Sep 17, 1985

Filed:

Feb 19, 1982

Appl. No.:

6/350513

Inventors:

Michael J. Patrick - Houston TX
David M. Snider - Cary NC

Assignee:

Texas Instruments Incorporated - Dallas TX
IBM Corp. - Dallas TX

International Classification:

G06F 900
G06F 700

US Classification:

364200

Abstract:

A single-chip microcomputer device contains on-chip program storage in a read-only memory (ROM), and this program may be corrected or updated by patching. The ROM addresses are applied to an off-chip memory device containing one bit for each potential ROM address, and each bit is set to mark the beginning address of code to be patched; an interrupt is signalled when one of these set bits is accessed by an address occurring during operation of the microcomputer. The interrupt causes the processor to branch to an off-chip program memory to insert the patch code. The patch ends in a branch back to the on-chip ROM.

US Patent:

45716757, Feb 18, 1986

Filed:

Jan 3, 1984

Appl. No.:

6/567599

Inventors:

Mark A. Stambaugh - Houston TX
Stephen P. Sacarisen - Houston TX
Michael W. Patrick - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 100

US Classification:

364200

Abstract:

A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i. e. , receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial. When the transmit-and-receive controller receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus, interrupting the local CPU.