Michael Stephen Pierce

US Patent:

7296408, Nov 20, 2007

Filed:

Sep 21, 2004

Appl. No.:

10/946228

Inventors:

Michael R. Pierce - Broomfield CO, US

International Classification:

F01B 29/10

US Classification:

60522, 60524

Abstract:

The heart of a heat engine is a reciprocating expansion chamber, which converts heat from a hot fluid into mechanical work. The expansion chamber utilizes a refrigerant in a liquid state as an input, and heats and expands the refrigerant to move pistons and generate work. A high pressure injector injects the liquid refrigerant into the chamber under enough pressure to keep it in a liquid state until it is desirable to have it expand into a gas. A hot fluid is the heat source for the expansion chamber and cold fluid is an output. Another output is the refrigerant, now a hot, low pressure gas. A compressor pressurizes the refrigerant, forming a hot, high pressure gas, and a condenser generates liquid refrigerant and provides it to the pressure injector.

US Patent:

20110167868, Jul 14, 2011

Filed:

Dec 28, 2010

Appl. No.:

12/979563

Inventors:

Michael C. Pierce - Erie CO, US
John D. Wilkinson - Midland TX, US
Hank M. Hudson - Midland TX, US

Assignee:

Ortloff Engineers, Ltd. - Midland TX

International Classification:

F25J 3/02

US Classification:

62620

Abstract:

A process and an apparatus are disclosed for recovering ethane, ethylene, and heavier hydrocarbon components from a hydrocarbon gas stream. The stream is cooled, expanded to lower pressure, and supplied to a first fractionation tower at a mid-column feed position. A distillation liquid stream is withdrawn from the first fractionation tower below the feed position of the expanded stream, heated, and directed into a second fractionation tower that produces an overhead vapor stream and a bottom liquid stream. The overhead vapor stream is cooled to condense it, with a portion of the condensed stream directed to the second fractionation tower as its top feed and the remainder directed to the first fractionation tower at a lower column feed position. The bottom liquid stream from the second fractionation tower is cooled and directed to the first fractionation tower as its top feed.

US Patent:

56067046, Feb 25, 1997

Filed:

Oct 26, 1994

Appl. No.:

8/330250

Inventors:

Michael E. Pierce - Orangevale CA
David C. Scheer - Boca Raton FL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

395750

Abstract:

A system for controlling the power consumption of an add-in PC card operating within a host computer. The host computer includes a power supply that provides all power used by the PC card. The PC card includes communication registers required for communication between the host computer and the PC card. The PC card also includes a microcontroller connected to an I/O subsystem and a multi-pin I/O connector. A first side of the multi-pin I/O connector is connected to the I/O subsystem and a second side is connected to a source of I/O signals external to the host computer. An external register module is connected to the microcontroller and communicates with the host computer. The external register module contains the communication registers. A status detector located on the PC card detects whether the I/O subsystem is processing I/O information, and supplies a status signal indicative thereof. A power management module is also located on the PC card and is connected to the status connector.

US Patent:

58025588, Sep 1, 1998

Filed:

Nov 6, 1996

Appl. No.:

8/746155

Inventors:

Michael E. Pierce - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06K 19067
G06F 1300
G06F 900

US Classification:

711115

Abstract:

An apparatus and a method for upgrading the memory contents of a removable computer card in a computer system. The computer card includes a specialized random access memory and circuitry that allows the computer system read only access to the contents of a first portion of the specialized random access memory device during normal operations. To upgrade the contents in the specialized random access memory, the circuitry allows the computer system write access privileges to the entire random access memory device. The computer card also includes a microcontroller which controls read and write access requests by the computer system to the specialized random access memory device. The microcontroller is placed in a reduced power consumption state when the computer system is performing read only access to the specialized random access memory device so that overall power consumption by the card in the computer system is reduced.

US Patent:

56641982, Sep 2, 1997

Filed:

Oct 26, 1994

Appl. No.:

8/329230

Inventors:

Chengwu Chen - Sacramento CA
Michael E. Pierce - Sacramento CA
James L. Foote - Sacramento CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314
G06F 1300

US Classification:

395733

Abstract:

A system for accessing attribute memory on a card using the interrupt capability of a microcontroller on the PCMCIA card intended to perform I/O functions for the host. The attribute memory interfaces directly with the microcontroller. A PLD is connected between the host bus and the microcontroller decodes the host's bus signals and generates an interrupt signal when it detects a request for access to the attribute memory which signal is supplied to the microcontroller. Upon receipt of the interrupt signal, the microcontroller runs a special routine that accesses attribute memory and supplies the results to the host. The PCMCIA card has a configured state in which the host has read the configuration information from attribute memory and has allocated necessary system resources. The PCMCIA card is in an unconfigured state if the foregoing has not been accomplished. The programmable logic device contains an AND gate having one of its inputs connected to the lines of the bus relating to the I/O function and a second input connected to the microprocessor for receiving a card enable signal, having at least two logic states.

US Patent:

55465900, Aug 13, 1996

Filed:

Sep 19, 1994

Appl. No.:

8/308835

Inventors:

Michael E. Pierce - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

395750

Abstract:

An apparatus and method for removing and applying power to circuitry within a Personal Computer Memory Card International Association (PCMCIA) PC card so as to reduce power consumption and, thus, prolong battery life for a portable computer system or electronic device, hereinafter referred to as a host system, in which the PC card is plugged is described. The PC card employs logic controlled by the host system to properly sequence control lines to and removal of power from the PC card circuitry to be powered down so as to prevent the occurrence of a CMOS latchup condition, allow for data to be saved and later restored when the circuitry is powered up, and maximize reduction in power consumption by the host system.

Address:

3860 Broadlands Ln, Broomfield, CO 80023

Phone:

7208413463

VIN:

1FMJU2A5XCEF53482

Make:

FORD

Model:

EXPEDITION

Year:

2012