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A filter module for reducing a DC offset voltage in a radio frequency communication channel is described. A first capacitor is coupled between a first differential input node and a first differential output node. A second capacitor is coupled between a second differential input node and a second differential output node. An active variable resistor is coupled between the first differential output node and the second differential output node. The active variable resistor receives a control signal. The control signal adjusts the value of the active variable resistor, which adjusts the frequency response of the filter module. The rate at which the filter module reduces DC offset voltages is thereby adjusted. The filter module is also adaptable to single-ended applications.
Method And Apparatus For A Parallel Correlator And Applications Thereof
Gregory S. Rawlins - Heathrow FL, US Michael W. Rawlins - Lake Mary FL, US David F. Sorrells - Middleburg FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
G06F 17/15
US Classification:
708425, 708314, 708319
Abstract:
A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X-X) with encoding coefficients (C-C), wherein each of (X-X) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, Xis multiplied by each state (Cthrough C) of the coefficient C, thereby generating results XCthrough XC. This is repeating for data bits (X-X) and corresponding coefficients (C-C), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.
Method And Apparatus For Reducing Dc Offsets In A Communication System
Gregory S. Rawlins - Heathrow FL, US Kevin Brown - Clermont FL, US Michael W. Rawlins - Lake Mary FL, US David F. Sorrells - Middleburg FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
H04B 1/10
US Classification:
375346, 375345
Abstract:
Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. The stored DC offset is subtracted from the receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. In a third aspect, a feedback loop circuit reduces DC offset in a WLAN receiver channel. The feedback loop circuit includes a storage element that samples and stores receiver channel DC offset. The loop is opened, and the DC offset stored in the storage element is subtracted from the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.
Method And Apparatus For Reducing Dc Offsets In A Communication System
Gregory S. Rawlins - Heathrow FL, US Michael W. Rawlins - Lake Mary FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
H03D 1/04
US Classification:
375346
Abstract:
Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.
Method And Apparatus For A Parallel Correlator And Applications Thereof
Gregory S. Rawlins - Heathrow FL, US Michael W. Rawlins - Lake Mary FL, US David F. Sorrells - Middleburg FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
G06F 17/15
US Classification:
708422, 708314, 708319
Abstract:
A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X–X) with encoding coefficients (C–C), wherein each of (X–X) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, Xis multiplied by each state (Cthrough C) of the coefficient C, thereby generating results XCthrough XC. This is repeating for data bits (X–X) and corresponding coefficients (C–C), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.
Active Polyphase Inverter Filter For Quadrature Signal Generation
Gregory L Milne - Winter Springs FL, US Michael W Rawlins - Lake Mary FL, US Gregory S Rawlins - Heathrow FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
H03D 3/22
US Classification:
375330, 375302
Abstract:
A quadrature signal generator receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature generator includes a coarse stage and a plurality of refinement stages. The coarse stage generates quadrature signals that may have some phase error, and the refinement stages process the quadrature signals to reduce any phase error. The refinement stages receive quadrature signals from the output of the coarse stage, and processes the quadrature signals to reduce the phase errors. The coarse stage and the refinement stages are configured using delay circuits that can be implemented with inverter circuits, such as, for example, CMOS inverter circuits. In the refinement stages, corresponding outputs of the delay stages are averaged together to reduce the quadrature phase error.
Method And Apparatus For The Parallel Correlator And Applications Thereof
Gregory S. Rawlins - Heathrow FL, US Michael W. Rawlins - Lake Mary FL, US David F. Sorrells - Middleburg FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
G06F 17/15
US Classification:
708422
Abstract:
A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X-X) with encoding coefficients (C-C), wherein each of (X-X) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, Xis multiplied by each state (Cthrough C) of the coefficient C, thereby generating results XCthrough XC. This is repeating for data bits (X-X) and corresponding coefficients (C-C), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.
Gregory S. Rawlins - Heathrow FL, US Kevin Brown - Clermont FL, US Michael W. Rawlins - Lake Mary FL, US David F. Sorrells - Middleburg FL, US
Assignee:
ParkerVision, Inc. - Jacksonville FL
International Classification:
H04L 27/08
US Classification:
375345
Abstract:
Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. The stored DC offset is subtracted from the receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. In a third aspect, a feedback loop circuit reduces DC offset in a WLAN receiver channel. The feedback loop circuit includes a storage element that samples and stores receiver channel DC offset. The loop is opened, and the DC offset stored in the storage element is subtracted from the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.
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