Michael A Rhoades

US Patent:

57377600, Apr 7, 1998

Filed:

Oct 6, 1995

Appl. No.:

8/539979

Inventors:

George G. Grimmer - Austin TX
Michael W. Rhoades - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

G06F 1214

US Classification:

711163

Abstract:

A microcontroller (20) provides security for internal instructions and data while allowing instruction fetches to external, off-chip memory connected to an expansion bus (30). A central processing unit (CPU) (21) provides a load instruction register signal to indicate when an access is an instruction fetch. When the load instruction register signal is active while the address is within the range of an on-chip nonvolatile memory (25), a security logic circuit (40) is reset to a first state. In this first state, the security logic circuit (40) also allows non-instruction fetches from the nonvolatile memory (25). However when the load instruction register signal is active while the address is not within the range of the nonvolatile memory (25), the security logic circuit (40) is set to a second state. While in this second state, the security logic circuit (40) disables attempted accesses to the nonvolatile memory (25). The security feature is selectively enabled or disabled as determined by a configuration register (23).