Michael J Rhoades

Address:

2002 Delvin Ln, Austin, TX 78728

VIN:

1HGFA16567L017749

Make:

HONDA

Model:

CIVIC

Year:

2007

US Patent:

7743184, Jun 22, 2010

Filed:

Aug 25, 2006

Appl. No.:

11/510369

Inventors:

James M. Sibigtroth - Round Rock TX, US
Michael W. Rhoades - Austin TX, US
Michael C. Wood - Pflugerville TX, US
George E. Baker - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00
G06F 3/00
G06F 13/14
G06F 13/28

US Classification:

710 52, 710 35, 710 55, 710 65, 710305, 711141

Abstract:

Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

US Patent:

8015329, Sep 6, 2011

Filed:

May 7, 2010

Appl. No.:

12/776281

Inventors:

James M. Sibigtroth - Round Rock TX, US
Michael W. Rhoades - Austin TX, US
Michael C. Wood - Pflugerville TX, US
George E. Baker - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00
G06F 3/00
G06F 13/14

US Classification:

710 52, 710 33, 710 35, 710305, 711141

Abstract:

Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

US Patent:

57377600, Apr 7, 1998

Filed:

Oct 6, 1995

Appl. No.:

8/539979

Inventors:

George G. Grimmer - Austin TX
Michael W. Rhoades - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

G06F 1214

US Classification:

711163

Abstract:

A microcontroller (20) provides security for internal instructions and data while allowing instruction fetches to external, off-chip memory connected to an expansion bus (30). A central processing unit (CPU) (21) provides a load instruction register signal to indicate when an access is an instruction fetch. When the load instruction register signal is active while the address is within the range of an on-chip nonvolatile memory (25), a security logic circuit (40) is reset to a first state. In this first state, the security logic circuit (40) also allows non-instruction fetches from the nonvolatile memory (25). However when the load instruction register signal is active while the address is not within the range of the nonvolatile memory (25), the security logic circuit (40) is set to a second state. While in this second state, the security logic circuit (40) disables attempted accesses to the nonvolatile memory (25). The security feature is selectively enabled or disabled as determined by a configuration register (23).

US Patent:

52513041, Oct 5, 1993

Filed:

Sep 28, 1990

Appl. No.:

7/589246

Inventors:

James M. Sibigtroth - Round Rock TX
Michael W. Rhoades - Austin TX
George G. Grimmer - Austin TX
Susan W. Longwell - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200
G06F 1214

US Classification:

395375

Abstract:

A data processor with memory within a single integrated circuit package provides a programmable "secure mode" of operation to selectively restrict access and protect information stored in its memory. The secure mode of operation is included in addition to a "single chip mode" wherein the data processor accesses both data and instructions strictly from within the single integrated circuit package. An "expanded mode" of operation also exists wherein the data processor may access either internal or external memory for both instructions and data. The secure mode of operation restricts accesses of instructions to memory contained within the single integrated circuit while allowing data accesses to memory either internal or external to the integrated circuit. The secure mode is accomplished by selectively isolating internal data/instruction bus transfer activity from an external data/instruction bus.