Michael W Rhodehamel

US Patent:

RE38388, Jan 13, 2004

Filed:

Jun 14, 2001

Appl. No.:

09/882444

Inventors:

Nitin V. Sarangdhar - Portland OR
Konrad K. Lai - Vancouver WA
Gurbir Singh - Gig Harbor WA
Peter D. MacWilliams - Aloha OR
Stephen S. Pawlowski - Beaverton OR
Michael W. Rhodehamel - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12417

US Classification:

710105, 710 39, 710111, 710112, 340 35, 34082552

Abstract:

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

US Patent:

7802083, Sep 21, 2010

Filed:

Dec 20, 2006

Appl. No.:

11/613317

Inventors:

Nagasubramanian Gurumoorthy - Portland OR, US
Michael Rhodehamel - Portland OR, US
Arvind Kumar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/445
G06F 15/173

US Classification:

713 1, 713 2, 709223, 709224, 717120, 717170, 717176, 717177, 717178

Abstract:

Methods, apparatuses, articles, and systems for performing an installation by a client system at a time when the client system is predicted to be below a level, are disclosed. The installation may be a software or a patch. In various embodiments, the methods, apparatus et al may include performance of the adaptive prediction, and the adaptive prediction may be performed by a learning algorithm. In other embodiments, the methods et al may also develop a model of the client system's utilization by observing and recording metrics of hardware and software utilization over time.

US Patent:

58451072, Dec 1, 1998

Filed:

Jul 3, 1996

Appl. No.:

8/675679

Inventors:

Matthew A. Fisch - Beaverton OR
James E. Jacobson - West Linn OR
Michael W. Rhodehamel - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1576

US Classification:

395500

Abstract:

A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

US Patent:

6009477, Dec 28, 1999

Filed:

Dec 17, 1998

Appl. No.:

9/213098

Inventors:

Nitin Sarangdhar - Beaverton OR
Michael Rhodehamel - Beaverton OR
Matthew Fisch - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

710 1

Abstract:

Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus. Wired-OR logic is employed for allowing an agent to transmit a state transition signal to all other agents on the bus changing the state of the various state machines only a single state transition signal is required to completely control the state of the state machines. By employing wired-OR logic, any particular agent is capable of switching the state machines into a stalled state to prevent new bus transactions from being issued to the bus.

US Patent:

57970262, Aug 18, 1998

Filed:

Sep 2, 1997

Appl. No.:

8/921845

Inventors:

Michael W. Rhodehamel - Beaverton OR
Nitin V. Sarangdhar - Woodland OR
Amit A. Merchant - Portland OR
Matthew A. Fisch - Beaverton OR
James M. Brayton - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

39580001

Abstract:

A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.

US Patent:

59012978, May 4, 1999

Filed:

Nov 19, 1997

Appl. No.:

8/974750

Inventors:

Matthew A. Fisch - Beaverton OR
Michael W. Rhodehamel - Beaverton OR
Nitin Sarangdhar - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13362

US Classification:

395294

Abstract:

An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent. Each agent performs this initialization based on its agent identification, the identity of the priority agent, and the maximum number of agents allowed on the bus.

US Patent:

58021329, Sep 1, 1998

Filed:

Sep 6, 1996

Appl. No.:

8/708928

Inventors:

Chakrapani Pathikonda - Beaverton OR
Matthew A. Fisch - Beaverton OR
Michael W. Rhodehamel - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 2100

US Classification:

377 48

Abstract:

A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

US Patent:

55155162, May 7, 1996

Filed:

Mar 1, 1994

Appl. No.:

8/205035

Inventors:

Matthew A. Fisch - Beaverton OR
Michael W. Rhodehamel - Beaverton OR
Nitin Sarangdhar - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13362

US Classification:

395294

Abstract:

An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent. Each agent performs this initialization based on its agent identification, the identity of the priority agent, and the maximum number of agents allowed on the bus.