Michael P Saunders

US Patent:

6941504, Sep 6, 2005

Filed:

Nov 15, 2001

Appl. No.:

09/998399

Inventors:

Michael Criscolo - Cedar Park TX, US
Pedro Martin-de-Nicolas - Austin TX, US
Charles Leverett Meissner - Austin TX, US
Michael Timothy Saunders - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M013/00

US Classification:

714758

Abstract:

The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.

US Patent:

6973607, Dec 6, 2005

Filed:

Nov 29, 2001

Appl. No.:

09/998390

Inventors:

Heinz Baier - Sindelfingen, DE
Robert Francis Berry - Round Rock TX, US
Michael Criscolo - Cedar Park TX, US
Pedro Martin-de-Nicolas - Austin TX, US
Michael Timothy Saunders - Round Rock TX, US
Kanti C. Shah - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28

US Classification:

714724, 710107

Abstract:

An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

US Patent:

6976199, Dec 13, 2005

Filed:

Jan 7, 2002

Appl. No.:

10/042080

Inventors:

Michael Timothy Saunders - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28

US Classification:

714726

Abstract:

In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.

US Patent:

7085980, Aug 1, 2006

Filed:

May 2, 2002

Appl. No.:

10/138894

Inventors:

Pedro Martin-de-Nicolas - Austin TX, US
Charles Leverett Meissner - Austin TX, US
Michael Timothy Saunders - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714736

Abstract:

The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i. e. , a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i. e. , a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

US Patent:

7457974, Nov 25, 2008

Filed:

Sep 8, 2005

Appl. No.:

11/221552

Inventors:

Christopher R. Conley - Pflugerville TX, US
Michael Criscolo - Cedar Park TX, US
Michael T. Saunders - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

713322, 713300, 713310, 713320, 713321, 713323, 713330, 713340

Abstract:

A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. When the motherboard powers up, the clock selector sends the peripheral device an external clock signal from the motherboard.

US Patent:

7620828, Nov 17, 2009

Filed:

Aug 6, 2008

Appl. No.:

12/187202

Inventors:

Michael Criscolo - Cedar Park TX, US
Michael T. Saunders - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340, 713600, 713601

Abstract:

A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. When the motherboard powers up, the clock selector sends the peripheral device an external clock signal from the motherboard.

US Patent:

7689865, Mar 30, 2010

Filed:

Sep 6, 2006

Appl. No.:

11/470478

Inventors:

Heinz Baier - Sindelfingen, DE
Christopher R. Conley - Pflugerville TX, US
Brian Flachs - Georgetown TX, US
Michael T. Saunders - Round Rock TX, US
Steven J. Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 30, 714 28

Abstract:

A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149. 1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

US Patent:

8347022, Jan 1, 2013

Filed:

Dec 18, 2008

Appl. No.:

12/339018

Inventors:

Robert W. Berry - Round Rock TX, US
Michael Criscolo - Cedar Park TX, US
Michael T. Saunders - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711103, 711154

Abstract:

A method comprises providing a golden ROM unit comprising known good ROM code. The golden ROM is coupled to a ROM socket of a target system. The target system is booted, wherein booting comprises providing power to the target system and independently providing power to the ROM socket. The known good ROM code is loaded from the golden ROM to a system memory of the target system. Power is removed from the ROM socket and the golden ROM is decoupled from the ROM socket. A first subject ROM is coupled to the ROM socket. Power is provided to the ROM socket and the first subject ROM is programmed with the known good ROM code.