Michael C Sebastian

US Patent:

7925931, Apr 12, 2011

Filed:

Dec 13, 2006

Appl. No.:

11/610469

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Mark A. Overby - Bothell WA, US
Andrew Currid - Alameda CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 43

Abstract:

Embodiments of the present invention provide a method for handling errors in data servers. Generally, embodiments of the invention enable a data packet that is marked as erroneous to be handled so that it is not committed to permanent storage. One or more components are configured to recognize a poisoned data indicator, and to respond to the indicator by taking programmed actions to delete the data, to stop the data from being transmitted, to notify upstream components, and to purge related data from downstream components.

US Patent:

8060774, Nov 15, 2011

Filed:

Jun 14, 2007

Appl. No.:

11/763365

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Suresh Natarajan Rajan - San Jose CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 11/00

US Classification:

714 5, 714 7, 714 8

Abstract:

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

US Patent:

8327104, Dec 4, 2012

Filed:

Nov 13, 2007

Appl. No.:

11/939440

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Daniel L. Rosenband - San Mateo CA, US
David T. Wang - San Jose CA, US
Suresh Natarajan Rajan - San Jose CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 13/00

US Classification:

711167, 711154

Abstract:

A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

US Patent:

8397013, Mar 12, 2013

Filed:

Mar 27, 2008

Appl. No.:

12/057306

Inventors:

Daniel L. Rosenband - San Mateo CA, US
Frederick Daniel Weber - San Jose CA, US
Michael John Sebastian Smith - Palo Alto CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 12/00
G11C 7/00

US Classification:

711103, 711104, 711105, 711111, 711148, 711154, 365205

Abstract:

One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.

US Patent:

8615679, Dec 24, 2013

Filed:

Sep 14, 2012

Appl. No.:

13/618246

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Suresh Natarajan Rajan - San Jose CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 11/00

US Classification:

714 51, 714 613

Abstract:

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

US Patent:

8631193, Jan 14, 2014

Filed:

May 17, 2012

Appl. No.:

13/473827

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Suresh Natarajan Rajan - San Jose CA, US
David T Wang - Thousand Oaks CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 12/00

US Classification:

711105, 711 5, 711167, 36518912

Abstract:

One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

US Patent:

20120042204, Feb 16, 2012

Filed:

Oct 24, 2011

Appl. No.:

13/280251

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Suresh Natarajan Rajan - San Jose CA, US

Assignee:

Google, Inc. - Mountain View CA

International Classification:

G06F 11/00

US Classification:

714 632, 714E11063

Abstract:

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

US Patent:

20130007399, Jan 3, 2013

Filed:

Sep 13, 2012

Appl. No.:

13/615008

Inventors:

Michael John Sebastian Smith - Palo Alto CA, US
Daniel L. Rosenband - Cambridge MA, US
David T. Wang - Thousand Oaks CA, US
Suresh Natarajan Rajan - San Jose CA, US

Assignee:

GOOGLE INC. - Mountain View CA

International Classification:

G06F 12/00

US Classification:

711167, 711E12001

Abstract:

A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.