Michael J Simone

US Patent:

56511248, Jul 22, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/478025

Inventors:

Gene W. Shen - Mountain View CA
John Szeto - Oakland CA
Niteen A. Patkar - Sunnyvale CA
Michael C. Shebanow - Plano TX
Michael A. Simone - Santa Clara CA

Assignee:

HAL Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1100

US Classification:

395391

Abstract:

Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.

US Patent:

57845867, Jul 21, 1998

Filed:

Aug 21, 1995

Appl. No.:

8/517229

Inventors:

Michael A. Simone - Sunnyvale CA
Michael C. Shebanow - Plano TX

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 930

US Classification:

395392

Abstract:

A method of permitting out of order execution of load instructions with respect to older store instructions in a general purpose computer evaluates whether the same data bytes are being accessed by both the store and load instructions and if they are not the same, then out of order execution of the load with respect to the store instructions is permitted.

US Patent:

56383126, Jun 10, 1997

Filed:

Mar 3, 1995

Appl. No.:

8/397800

Inventors:

Michael A. Simone - Sunnyvale CA

Assignee:

HaL Computer Systems, Inc. - Campbell CA

International Classification:

G06F 700
G06F 738

US Classification:

3647365

Abstract:

A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first performs a zero detect on each byte of data retrieved from memory. The zero detect results are next decoded according to bit selection signals generated from a data format code which corresponds to the specific format of the retrieved data.