Michael D Steigerwalt

US Patent:

6900092, May 31, 2005

Filed:

Jun 27, 2002

Appl. No.:

10/183336

Inventors:

Atul C. Ajmera - Wappingers Falls NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/8238
H01L021/336
H01L021/3205
H01L021/31

US Classification:

438231, 438300, 438592, 438586, 438776, 438792

Abstract:

The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

US Patent:

6964897, Nov 15, 2005

Filed:

Jun 9, 2003

Appl. No.:

10/250157

Inventors:

Karen A. Bard - Hopewell Junction NY, US
David M. Dobuzinsky - New Windsor NY, US
Herbert L. Ho - New Windsor NY, US
Mahendar Kumar - Fishkill NY, US
Denise Pendleton - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US
Brian L. Walsh - New Paltz NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/8242

US Classification:

438243

Abstract:

A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

US Patent:

6995094, Feb 7, 2006

Filed:

Oct 13, 2003

Appl. No.:

10/605607

Inventors:

Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Brian Messenger - Newburgh NY, US
Michael D. Steigerwalt - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302

US Classification:

438710, 438717, 438719, 438723, 438724, 438735, 438736, 438738, 438743, 216 47, 216 51, 216 74, 216 79, 216 80

Abstract:

A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.

US Patent:

7115463, Oct 3, 2006

Filed:

Aug 20, 2004

Appl. No.:

10/923246

Inventors:

Devendra K. Sadana - Pleasantville NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/762

US Classification:

438218, 438219, 438405, 438407, 438524, 438526, 438528, 257E21564, 257E21563

Abstract:

The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

US Patent:

7115965, Oct 3, 2006

Filed:

Sep 1, 2004

Appl. No.:

10/931855

Inventors:

Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/70

US Classification:

257526, 257347, 257350, 257370, 257565, 257592

Abstract:

The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

US Patent:

7118986, Oct 10, 2006

Filed:

Jun 16, 2004

Appl. No.:

10/710060

Inventors:

Michael D. Steigerwalt - Newburgh NY, US
Mahender Kumar - Fishkill NY, US
Herbert L. Ho - New Windsor NY, US
David M. Dobuzinsky - New Windsor NY, US
Johnathan E. Faltermeier - LaGrangeville NY, US
Denise Pendleton - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/76

US Classification:

438424, 438151, 257347, 257348, 257349, 257350

Abstract:

Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

US Patent:

7375410, May 20, 2008

Filed:

Feb 25, 2004

Appl. No.:

10/787002

Inventors:

Herbert L. Ho - New Windsor NY, US
Mahender Kumar - Fishkill NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Paul A. Papworth - Wappingers Falls NY, US
Christopher D. Sheraw - Wappingers Falls NY, US
Michael D. Steigerwalt - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/102

US Classification:

257526, 257587, 257592, 257E29183, 257E2919, 257E29198

Abstract:

The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

US Patent:

7394131, Jul 1, 2008

Filed:

Jun 21, 2006

Appl. No.:

11/425467

Inventors:

Michael D. Steigerwalt - Newburgh NY, US
Mahender Kumar - Fishkill NY, US
Herbert L. Ho - New Windsor NY, US
David M. Dobuzinsky - New Windsor NY, US
Johnathan E. Faltermeier - LaGrangeville NY, US
Denise Pendleton - Wappinger Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/01

US Classification:

257347, 257506

Abstract:

Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.