Michael D Swift

US Patent:

6617104, Sep 9, 2003

Filed:

Dec 3, 1997

Appl. No.:

08/984090

Inventors:

Michael R. Swift - Scarsdale NY 10583

International Classification:

C12Q 168

US Classification:

435 6, 435 911, 435 912, 536 231, 536 235, 536 2431, 536 2433

Abstract:

The present invention relates generally to the field of human genetics. Specifically, the present invention relates to the discovery that some alleles of the A-T gene cause susceptibility to cancer, in particular breast cancer. More specifically, the present invention relates to germline mutations in the A-T gene and their use in the diagnosis of predisposition to breast cancer. The invention further relates to somatic mutations in the A-T gene in human breast cancer and their use in the diagnosis and prognosis of human breast cancer.

US Patent:

20030148364, Aug 7, 2003

Filed:

Feb 11, 2003

Appl. No.:

10/361562

Inventors:

Michael Swift - Scarsdale NY, US
Prasanna Athma - Yorktown Heights NY, US
Alrong Li - Hastings-on-Hudson NY, US

International Classification:

C12Q001/68
C12P019/34

US Classification:

435/006000, 435/091200

Abstract:

The present invention relates generally to the field of human genetics. Specifically, the present invention relates to the discovery that some alleles of the A-T gene cause susceptibility to cancer, in particular breast cancer. More specifically, the present invention relates to germline mutations in the A-T gene and their use in the diagnosis of predisposition to breast cancer. The invention further relates to somatic mutations in the A-T gene in human breast cancer and their use in the diagnosis and prognosis of human breast cancer.

US Patent:

20210074053, Mar 11, 2021

Filed:

Nov 19, 2020

Appl. No.:

16/953021

Inventors:

- Cupertino CA, US
Michael J. Swift - Brooklyn NY, US
Michal Valient - San Jose CA, US
Robert S. Hartog - Windermere CA, US
Tyson J. Bergland - Sunnyvale CA, US
Gokhan Avkarogullari - San Jose CA, US

International Classification:

G06T 15/04
G06T 1/60
G06F 9/38
G06T 11/00
G06F 12/1009
G06F 9/50
G06T 15/00
G06F 12/0811

Abstract:

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

US Patent:

20210064539, Mar 4, 2021

Filed:

May 15, 2020

Appl. No.:

16/874997

Inventors:

- Cupertino CA, US
Bernard Joseph Semeria - Palo Alto CA, US
Michael J. Swift - Brooklyn NY, US
Pradeep Kanapathipillai - Santa Clara CA, US
David J. Williamson - Austin TX, US

International Classification:

G06F 12/1009
G06F 12/1072
G06F 12/0873
G06F 12/14

Abstract:

A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

US Patent:

20200104968, Apr 2, 2020

Filed:

Nov 28, 2018

Appl. No.:

16/202689

Inventors:

- Cupertino CA, US
Michael J. Swift - Brooklyn NY, US

International Classification:

G06T 1/20
G06T 1/60

Abstract:

Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

US Patent:

20180181489, Jun 28, 2018

Filed:

Dec 22, 2016

Appl. No.:

15/389047

Inventors:

- Cupertino CA, US
Owen C. Anderson - San Jose CA, US
Michael J. Swift - Brooklyn NY, US
Aaftab A. Munshi - Los Gatos CA, US
Terence M. Potter - Austin TX, US

International Classification:

G06F 12/0815
G06F 12/0811
G06F 12/084

Abstract:

Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.