Michael A Tripp

US Patent:

7328359, Feb 5, 2008

Filed:

Jul 21, 2004

Appl. No.:

10/897225

Inventors:

Tim Frodsham - Portland OR, US
Michael J. Tripp - Forest Grove OR, US
David J. O'Brien - Portland OR, US
Muraleedhara Navada - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David S. Dunning - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/04
G06F 1/12
G06F 5/00
G06F 13/42
H04L 7/00

US Classification:

713400, 713401, 713500, 713501, 713502, 713503

Abstract:

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

US Patent:

7463992, Dec 9, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/540840

Inventors:

Samie B. Samaan - Lake Oswego OR, US
Victor Zia - Beaverton OR, US
Michael Tripp - Forest Grove OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

702118

Abstract:

A method, apparatus, article of manufacture, and system, the method including, in some embodiments, performing an in-system (or in-the-field) self-test on a first core of a multi-core (or multi-CPU) processor to obtain at a value for at least one operational parameter of the first core, storing the value for the at least one operational parameter of the first core, testing, under control of the first core, at least one of a remaining set of cores of the multi-core processor to determine a value for the at least one operational parameter for the at least one core of the remaining set of cores, and testing, under control of the at least one core of the remaining set of cores, the first core to determine a value for the at least one operational parameter for the first core.

US Patent:

7747888, Jun 29, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/978849

Inventors:

Tim Frodsham - Portland OR, US
Michael J. Tripp - Forest Grove OR, US
David J. O'Brien - Portland OR, US
Muraleedhara Navada - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David S. Dunning - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/12
G06F 1/14

US Classification:

713400, 713401, 713502, 713503, 375356, 375357

Abstract:

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

US Patent:

20060168379, Jul 27, 2006

Filed:

Dec 13, 2004

Appl. No.:

11/011301

Inventors:

Tim Frodsham - Portland OR, US
Michael Tripp - Forest Grove OR, US
David O'Brien - Portland OR, US
Navada Muraleedhara - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David Dunning - Portland OR, US
Theodore Schoenborn - Portland OR, US

International Classification:

G06F 13/00

US Classification:

710107000

Abstract:

A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.

US Patent:

6615379, Sep 2, 2003

Filed:

Dec 8, 1999

Appl. No.:

09/457255

Inventors:

Michael J. Tripp - Forest Grove OR
James W. Alexander - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714736, 324765

Abstract:

Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test. If the signatures match, a gating signal is provided so that additional test vectors are applied to the device or system under test.

US Patent:

20140156892, Jun 5, 2014

Filed:

Jun 10, 2013

Appl. No.:

13/913774

Inventors:

Tim Frodsham - Portland OR, US
Michael J. Tripp - Forest Grove OR, US
David J. O'Brien - Portland OR, US
Navada Herur Muraleedhara - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David S. Dunning - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US

International Classification:

G06F 1/06
G06F 13/362

US Classification:

710110

Abstract:

A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.