Michael John Tripp

US Patent:

6721216, Apr 13, 2004

Filed:

Mar 30, 2001

Appl. No.:

09/823597

Inventors:

Tak M. Mak - Union City CA
Michael R. Spica - Hillsboro OR
Michael J. Tripp - Forest Grove OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 2900

US Classification:

365201, 36523006, 36518905, 365233, 714718

Abstract:

An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.

US Patent:

6757209, Jun 29, 2004

Filed:

Mar 30, 2001

Appl. No.:

09/823642

Inventors:

Tak M. Mak - Union City CA
Michael R. Spica - Hillsboro OR
Michael J. Tripp - Forest Grove OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

36523002, 36518902, 36523006

Abstract:

An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.

US Patent:

6885209, Apr 26, 2005

Filed:

Aug 21, 2002

Appl. No.:

10/224492

Inventors:

Tak M. Mak - Union City CA, US
Michael J. Tripp - Forest Grove OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R031/02
H04B017/00
H04B003/46
H04Q001/20

US Classification:

324763, 375219, 375226, 375376

Abstract:

A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.

US Patent:

7139957, Nov 21, 2006

Filed:

Jun 30, 2003

Appl. No.:

10/611099

Inventors:

Bruce Querbach - Orangevale CA, US
David G. Ellis - Tualatin OR, US
Amjad Khan - Folsom CA, US
Michael J. Tripp - Forest Grove OR, US
Eric S. Gayles - Folsom CA, US
Eshwar Gollapudi - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/28
G11C 29/00

US Classification:

714745, 714721, 714724

Abstract:

A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

US Patent:

7328359, Feb 5, 2008

Filed:

Jul 21, 2004

Appl. No.:

10/897225

Inventors:

Tim Frodsham - Portland OR, US
Michael J. Tripp - Forest Grove OR, US
David J. O'Brien - Portland OR, US
Muraleedhara Navada - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David S. Dunning - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/04
G06F 1/12
G06F 5/00
G06F 13/42
H04L 7/00

US Classification:

713400, 713401, 713500, 713501, 713502, 713503

Abstract:

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

US Patent:

7463992, Dec 9, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/540840

Inventors:

Samie B. Samaan - Lake Oswego OR, US
Victor Zia - Beaverton OR, US
Michael Tripp - Forest Grove OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

702118

Abstract:

A method, apparatus, article of manufacture, and system, the method including, in some embodiments, performing an in-system (or in-the-field) self-test on a first core of a multi-core (or multi-CPU) processor to obtain at a value for at least one operational parameter of the first core, storing the value for the at least one operational parameter of the first core, testing, under control of the first core, at least one of a remaining set of cores of the multi-core processor to determine a value for the at least one operational parameter for the at least one core of the remaining set of cores, and testing, under control of the at least one core of the remaining set of cores, the first core to determine a value for the at least one operational parameter for the first core.

US Patent:

7747888, Jun 29, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/978849

Inventors:

Tim Frodsham - Portland OR, US
Michael J. Tripp - Forest Grove OR, US
David J. O'Brien - Portland OR, US
Muraleedhara Navada - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David S. Dunning - Portland OR, US
Theodore Z. Schoenborn - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/12
G06F 1/14

US Classification:

713400, 713401, 713502, 713503, 375356, 375357

Abstract:

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

US Patent:

20060168379, Jul 27, 2006

Filed:

Dec 13, 2004

Appl. No.:

11/011301

Inventors:

Tim Frodsham - Portland OR, US
Michael Tripp - Forest Grove OR, US
David O'Brien - Portland OR, US
Navada Muraleedhara - Santa Clara CA, US
Naveen Cherukuri - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
David Dunning - Portland OR, US
Theodore Schoenborn - Portland OR, US

International Classification:

G06F 13/00

US Classification:

710107000

Abstract:

A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.