Michael L Tubbs

US Patent:

60414014, Mar 21, 2000

Filed:

Feb 27, 1998

Appl. No.:

9/032429

Inventors:

Jens K. Ramsey - Houston TX
Jeffrey C. Stevens - Spring TX
Michael E. Tubbs - Montgomery TX
Charles J. Stancil - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200

US Classification:

712 43

Abstract:

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs).

US Patent:

58130225, Sep 22, 1998

Filed:

Aug 28, 1996

Appl. No.:

8/703927

Inventors:

Jens K. Ramsey - Houston TX
Jeffrey C. Stevens - Spring TX
Michael E. Tubbs - Montgomery TX
Charles J. Stancil - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200
G06F 132

US Classification:

711 3

Abstract:

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs).