Michael W Wolf

US Patent:

6345297, Feb 5, 2002

Filed:

May 26, 2000

Appl. No.:

09/578683

Inventors:

Steven Michael Grimm - Mountain View CA
Jeffrey Jackiel Rothschild - Los Gatos CA
Daniel Joseph Samuel - Sunnyvale CA
Michael Andrew Wolf - Mountain View CA

Assignee:

HearMe - Mountain View CA

International Classification:

G06F 1516

US Classification:

709227, 709204, 463 42

Abstract:

A network match making system and method is used to match users of a multi-users networked application. Each user is associated with a client computer connected to the network. Clients are selected based on attributes of their users, the clients, servers, and/or communication links. The network match maker works with three different forms of network applications: peer-to-peer, multiple clients to a single server, and multiple clients to multiple servers. In one match maker method, a client computer and one multi-user application server are matched. A list of multi-user application servers connected to the computer network that are available for a match is received. At least one communication attribute of respective data communication links between the client computer and a plurality of multi-application servers in the received list is measured. An additional attribute, such as a server attribute, is received from at least one of the plurality of multi-user application servers. A subset of one or more multi-user application servers is then selected based on the measured communication attributes and the additional attribute received from the multi-user application servers.

US Patent:

7647458, Jan 12, 2010

Filed:

Apr 8, 2008

Appl. No.:

12/082239

Inventors:

Gil Tene - Los Altos Hills CA, US
Michael A. Wolf - San Francisco CA, US

Assignee:

Azul Systems, Inc. - Mountain View CA

International Classification:

G06F 12/00

US Classification:

711159, 707200, 707206

Abstract:

A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage collection barrier instruction; wherein the processor is configured to execute the garbage collection barrier instruction, including by: evaluating a memory reference to determine a condition associated with the garbage collection barrier instruction; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

US Patent:

7689782, Mar 30, 2010

Filed:

Dec 6, 2005

Appl. No.:

11/296195

Inventors:

Jack Choquette - Mountain View CA, US
Gil Tene - Los Altos Hills CA, US
Michael A. Wolf - San Francisco CA, US

Assignee:

Azul Systems, Inc. - Mountain View CA

International Classification:

G06F 13/00

US Classification:

711152, 711153, 711173, 707206, 712244

Abstract:

An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

US Patent:

7836280, Nov 16, 2010

Filed:

Sep 14, 2005

Appl. No.:

11/227418

Inventors:

Gil Tene - Los Altos Hills CA, US
Ivan Posva - Menlo Park CA, US
Michael A. Wolf - San Francisco CA, US
Daniel Dwight Grove - San Jose CA, US
Tom Kraljevic - San Jose CA, US

Assignee:

Azul Systems, Inc. - Mountain View CA

International Classification:

G06F 9/00

US Classification:

712216, 712218

Abstract:

Executing a set of one or more instructions atomically is disclosed. Executing includes determining whether speculatively executing the instructions is advised based at least in part on dynamic information associated with synchronization data and speculatively executing the instructions when it is determined that speculatively executing the instructions is advised.

US Patent:

7840785, Nov 23, 2010

Filed:

Sep 14, 2005

Appl. No.:

11/227417

Inventors:

Gil Tene - Los Altos Hills CA, US
Michael A. Wolf - San Francisco CA, US

Assignee:

Azul Systems, Inc. - Mountain View CA

International Classification:

G06F 9/00

US Classification:

712220, 712 E905

Abstract:

Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.

US Patent:

7865701, Jan 4, 2011

Filed:

Sep 14, 2005

Appl. No.:

11/227422

Inventors:

Gil Tene - Los Altos Hills CA, US
Ivan Posva - Menlo Park CA, US
Michael A. Wolf - San Francisco CA, US
Daniel Dwight Grove - San Jose CA, US
Tom Kraljevic - San Jose CA, US

Assignee:

Azul Systems, Inc. - Mountain View CA

International Classification:

G06F 9/00

US Classification:

712220, 712228, 718106

Abstract:

Executing a set one or more instructions atomically is disclosed. Executing includes saving a set of one or more register states in a software data structure, speculatively executing the set of instructions, and restoring the state of one or more registers when an abort indication is received.

US Patent:

7987473, Jul 26, 2011

Filed:

Sep 14, 2005

Appl. No.:

11/227419

Inventors:

Gil Tene - Los Altos Hills CA, US
Murali Sundaresan - Sunnyvale CA, US
Michael A. Wolf - San Francisco CA, US

Assignee:

Azul Systems, Inc. - Sunnyvale CA

International Classification:

G06F 9/42

US Classification:

719320, 719331, 719332, 717116, 717148, 717153

Abstract:

Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

US Patent:

8037482, Oct 11, 2011

Filed:

Dec 6, 2005

Appl. No.:

11/296652

Inventors:

Gil Tene - Los Altos Hills CA, US
Murali Sundaresan - Sunnyvale CA, US
Michael A. Wolf - San Francisco CA, US

Assignee:

Azul Systems, Inc. - Sunnyvale CA

International Classification:

G06F 9/42

US Classification:

719321, 719320, 719331, 719332, 717116, 717148, 717153

Abstract:

Reaching a determination associated with a class of an object is disclosed. An identifier associated with the class of the object is extracted from a pointer to the object. The extracted identifier is compared to a comparison value. At least in part using a result of the comparison a determination is reached.