Michele E Young

US Patent:

49393910, Jul 3, 1990

Filed:

Jul 12, 1988

Appl. No.:

7/217942

Inventors:

Michele Young - San Francisco CA
Kapil Shankar - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 1760

US Classification:

307465

Abstract:

A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or a output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

US Patent:

47587474, Jul 19, 1988

Filed:

May 30, 1986

Appl. No.:

6/868970

Inventors:

Michele Young - San Francisco CA
Kapil Shankar - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19177
H03K 19092

US Classification:

307465

Abstract:

A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or an output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

US Patent:

51681773, Dec 1, 1992

Filed:

Oct 25, 1990

Appl. No.:

7/603817

Inventors:

Kapil Shankar - San Jose CA
Om P. Agrawal - San Jose CA
Fares Mubarak - Fremont CA
Michele Young - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

307465

Abstract:

A device having a number of general registers each allocated an input/output port and a number of internal "buried" state registers. A user-controlled signal permits observation of the contents of the buried state registers at an input/output port although these registers are not allocated an input/output port. Each register is connected to a logic circuit internal to the device by a dedicated feedback path so that all registers can be used to specify states in a state machine sequencer. A fuse-programmable XOR gate permits a user to control generation of signals at the ports by permitting enabling and disabling of an inverting output buffer. Asynchronous reset and synchronous preset of the registers is provided. In addition to the dedicated feedback paths, programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an externasl pin.