Mickey R Henniger

age ~63

from Nederland, CO

Also known as:
  • Mickey Ramal Henniger
  • Mickey Ramas Henniger
  • Mick R Henniger
  • Mickey Ramal Henninger
Phone and address:
7089 Magnolia Dr, Nederland, CO 80466

Mickey Henniger Phones & Addresses

  • 7089 Magnolia Dr, Nederland, CO 80466
  • Lometa, TX
  • Buchanan Dam, TX
  • 10906 Marble Rd, Austin, TX 78750 • 5124286474
  • Boulder, CO
  • Honolulu, HI
  • Round Rock, TX
  • Sunnyvale, CA
Name / Title
Company / Classification
Phones & Addresses
Mickey Henniger
Manager
HENNIGER INVESTMENTS, LLC
Investor
2250 Floral Dr, Boulder, CO 80304
10906 Marble Rd, Austin, TX 78750

Us Patents

  • Node Dependent Wireless Transmit Antenna Selection Technique

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  • US Patent:
    7515940, Apr 7, 2009
  • Filed:
    Mar 22, 2005
  • Appl. No.:
    11/086489
  • Inventors:
    Ming Chi Chen - Union City CA, US
    Mickey Ramal Henniger - Buchanan Dam TX, US
  • Assignee:
    Cisco Technology, Inc. - San Jose CA
  • International Classification:
    H04M 1/00
  • US Classification:
    4555621, 455101, 375299
  • Abstract:
    A system and method for selecting a best transmit antenna for a transceiver using antenna diversity that caches the identity of the best transmit antenna for each remote node from which a message has been received. The best transmit antenna is then selected for each message sent to a remote node having a cache entry.
  • Resuming A Computing Session When Rebooting A Computing Device

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  • US Patent:
    7533178, May 12, 2009
  • Filed:
    Oct 31, 2006
  • Appl. No.:
    11/591249
  • Inventors:
    Mickey Henniger - Buchanan Dam TX, US
  • Assignee:
    Cisco Technology, Inc. - San Jose CA
  • International Classification:
    G06F 15/16
    G06F 12/00
  • US Classification:
    709227, 713 2
  • Abstract:
    Methods and apparatus are disclosed for transparently resuming the network connection after a reset or reboot. In one aspect a data processing apparatus comprises an operating system unit configured to create and store state information comprising one or more parameters for a network connection between a first computing device and a second computing device; a management interface unit configured to receive a request to reboot the first computing device; and host reset session resumption logic configured to store, in response to the request, the state information in a particular location in a memory of the first computing device, to initiate a reboot of the first computing device, to retrieve the state information from the particular location in memory, and to request resuming data communications over the network connection based on the retrieved state information.
  • Backward-Compatible Parallel Ddr Bus For Use In Host-Daughtercard Interface

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  • US Patent:
    20050086409, Apr 21, 2005
  • Filed:
    Oct 17, 2003
  • Appl. No.:
    10/688446
  • Inventors:
    James Grishaw - Santa Clara CA, US
    Mickey Henniger - Buchanan Dam TX, US
  • International Classification:
    G06F013/00
  • US Classification:
    710301000
  • Abstract:
    A host-daughtercard interface is pin compatible with a legacy interface but redefines a subset of pins to implement a high-bandwidth double data-rate (DDR) bus. By inspecting a cookie on the daughtercard, the host platform determines whether the daughtercard supports the DDR bus or the legacy interface, and then configures the subset of pins to implement the legacy interface or the DDR bus.
  • Smart Card Functionality From A Security Co-Processor And Symmetric Key In Rom

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  • US Patent:
    20060075254, Apr 6, 2006
  • Filed:
    Sep 27, 2004
  • Appl. No.:
    10/952228
  • Inventors:
    Mickey Henniger - Buchanan Dam TX, US
  • International Classification:
    H04K 1/00
  • US Classification:
    713184000
  • Abstract:
    Smart card functionality is implemented utilizing a security co-processor already included on a device and external memory. An internal private key is stored in NVROM on the die of the security co-processor and a private RAM, accessible by only the security co-processor, is also included. Blocks of data stored in external memory can be encrypted and decrypted using the private key. If other secret or symmetric keys are included in a block of data they are stored in clear text in the private RAM after decryption by the private internal key. The CPU can then request the security co-processor to encrypt/decrypt data using other secret or symmetric keys held in the private RAM.

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