Min Chen

US Patent:

20220270938, Aug 25, 2022

Filed:

Feb 19, 2021

Appl. No.:

17/180652

Inventors:

- San Diego CA, US
De LU - San Diego CA, US
Baldeo Sharan SHARMA - Bangalore, IN
Peeyush Kumar PARKAR - Bangalore, IN
Venkat NARAYANAN - San Diego CA, US
Rui LI - San Diego CA, US
Samy Shafik Tawfik ZAYNOUN - San Diego CA, US
Min CHEN - San Diego CA, US
David KIDD - San Diego CA, US
Amit PATIL - Bengaluru, IN

International Classification:

H01L 21/66
G06F 30/398

Abstract:

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

US Patent:

20200264229, Aug 20, 2020

Filed:

Feb 15, 2019

Appl. No.:

16/277543

Inventors:

- San Diego CA, US
Madan M. KRISHNAPPA - Bangalore, IN
Shih-Hsin Jason HU - San Diego CA, US
Min CHEN - San Marcos CA, US

International Classification:

G01R 31/28
G01R 31/00
H03K 3/03

Abstract:

Aspects of the present disclosure provide techniques for predicting a failure of an integrated circuit, which may include receiving first aging sensor data during an idle state of the integrated circuit; determining a voltage compensation value based on the first aging sensor data; comparing a new voltage value based on the voltage compensation value to a threshold operating voltage; determining the new operating voltage value exceeds the threshold operating voltage; determining a warning state for the integrated circuit; receiving second aging sensor data during the idle state of the integrated circuit; receiving stored aging sensor data from an aging sensor data repository; comparing the second aging sensor data to the stored aging sensor data; determining that the second aging sensor data is inconsistent with the stored aging sensor data; and determining a danger state for the integrated circuit.

US Patent:

20180143853, May 24, 2018

Filed:

Jan 5, 2017

Appl. No.:

15/398864

Inventors:

- San Diego CA, US
Niladri Mojumder - San Diego CA, US
Min Chen - San Marcos CA, US
Rajat Mittal - San Francisco CA, US
Rajit Chandra - Cupertino CA, US

International Classification:

G06F 9/48
G06F 9/445

Abstract:

A system includes a computer processor including N cores; and a plurality of device aging sensors, wherein each one of the plurality of device aging sensors is disposed within a respective core, the plurality of device aging sensors being configured to communicate core aging information with a core scheduler in the computer processor, wherein the core scheduler is configured to make a first set of M cores available to a thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a first time period in which the core aging information indicates that aging of the first set of M cores is below a threshold, and wherein the core scheduler is configured to make a second set of M cores available to the thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a second time period.

US Patent:

20180034452, Feb 1, 2018

Filed:

Sep 20, 2016

Appl. No.:

15/271007

Inventors:

- San Diego CA, US
Nan Chen - San Diego CA, US
Min Chen - San Marcos CA, US

International Classification:

H03K 5/156
H03K 21/02
H03K 3/03

Abstract:

Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency of an NMOS-based ring oscillator on a chip, and determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator. The method also includes measuring a frequency of a PMOS-based ring oscillator on the chip, and determining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator.

US Patent:

20160202953, Jul 14, 2016

Filed:

Jan 14, 2015

Appl. No.:

14/597146

Inventors:

- San Diego CA, US
Junmou Zhang - San Diego CA, US
Min Chen - San Marcos CA, US

International Classification:

G06F 7/58
G11C 11/417

Abstract:

One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.