Ming Wei Chen

US Patent:

6950355, Sep 27, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/020208

Inventors:

Surya Battacharya - Irvine CA, US
Ming Chen - Mission Viejo CA, US
Liming Tsau - Irvine CA, US
Henry Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

365201, 365154

Abstract:

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e. g. , wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

US Patent:

20030034489, Feb 20, 2003

Filed:

Jul 16, 2002

Appl. No.:

10/195527

Inventors:

Surya Bhattacharya - Irvine CA, US
Ming Chen - Newport Coast CA, US
Liming Tsau - Irvine CA, US
Henry Chen - Irvine CA, US
Neal Kistler - Monarch Beach CA, US
Yi Liu - Union City CA, US
Tzu-Hsin Huang - San Jose CA, US

Assignee:

Broadcom Corporation

International Classification:

H01L023/58

US Classification:

257/048000

Abstract:

A semiconductor wafer configured for in-process testing of integrated circuitry fabricated thereon. At least two die are separated by a scribe area, and each of the die has at least one complementary metal oxide silicon (CMOS) static random access memory (SRAM) array embedded therein among mixed-signal CMOS circuitry. The mixed-signal CMOS circuitry includes devices with larger feature sizes compared to similar devices of the embedded SRAM array. A first process control monitor (PCM) testline is included, which has a first layout corresponding to the mixed-signal CMOS circuitry. Additionally, a second PCM testline is included, which has a second layout corresponding to the embedded SRAM arrays. The first and second PCM testlines are formed in the scribe area.