Ming Z Li

US Patent:

7073952, Jul 11, 2006

Filed:

Jun 5, 2002

Appl. No.:

10/163405

Inventors:

Frank Xi Wu - Fremont CA, US
Jian Xu - Pleasanton CA, US
Ming Li - Pleasanton CA, US
Song Peng - Pleasanton CA, US

Assignee:

Avanex Corporation - Fremont CA

International Classification:

G02B 6/26
G02B 7/00

US Classification:

385 62, 385 90, 385 28, 359896, 24828831

Abstract:

An optical alignment device holds fiber collimators in place with extremely good mechanical and environmental stability. The device includes a ball with a hole traversing the ball, an upper clamping block with a first inner concave spherical surface and a lower clamping block with a second inner concave spherical surface. The hole includes a shape that can accommodate or contact an optical component whose alignment is to be controlled. The ball, together with the enclosed optical component is firmly held between the first and second inner concave surfaces of the clamping blocks, which are tightened against the ball with screws. When firmly clamped within the concave surfaces, the ball is prevented from accidental movement but can still rotate about any axis to align the optical component. Once alignment is achieved, the optical component and the ball are secured in place by epoxy, glue, solder or other suitable adhesive.

US Patent:

7705445, Apr 27, 2010

Filed:

Feb 11, 2005

Appl. No.:

11/056535

Inventors:

Ming Li - Fremont CA, US
Sayeh Khalili - San Jose CA, US
Donald R. Mullen - Mountain View CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H01L 23/14

US Classification:

257700, 257774, 257E23067

Abstract:

The semiconductor package includes two electrical contacts and a semiconductor device coupled to opposing sides of a substrate. The substrate defines at least one via extending at least partially there through. The semiconductor device includes a semiconductor low-speed interface electrically coupled to one of the electrical contacts through the via, and a semiconductor high-speed interface electrically coupled to flexible tape. The flexible tape is also electrically coupled to the other one of the electrical contacts.

US Patent:

7846793, Dec 7, 2010

Filed:

Oct 3, 2007

Appl. No.:

11/866625

Inventors:

Christopher S. Olsen - Fremont CA, US
Sean Seutter - San Jose CA, US
Ming Li - Watervliet NY, US
Phillip Allan Kraus - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/336
H01L 21/3105
H01L 21/4757

US Classification:

438260, 438710, 438723, 438783

Abstract:

A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide.

US Patent:

8063481, Nov 22, 2011

Filed:

Feb 20, 2008

Appl. No.:

12/526234

Inventors:

Ming Li - Fremont CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H01L 21/00

US Classification:

257700, 257713, 257720, 257723, 257E23039, 257E23083

Abstract:

The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i. e. , no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side.

US Patent:

8233303, Jul 31, 2012

Filed:

Dec 13, 2007

Appl. No.:

12/519353

Inventors:

Scott C. Best - Palo Alto CA, US
Ming Li - Fremont CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

G11C 5/02

US Classification:

365 51, 365 63

Abstract:

An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.

US Patent:

8415788, Apr 9, 2013

Filed:

Aug 20, 2010

Appl. No.:

12/860811

Inventors:

Ming Li - Fremont CA, US
Donald R. Mullen - Mountain View CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H05K 7/20

US Classification:

257723, 257712, 257720, 257774, 361709, 361717

Abstract:

A system includes a circuit board, a multi-die package, and a heat dissipator. The circuit board has substantially planar opposing first and second sides. The multi-die package includes a substrate and a first set of one or more semiconductor devices on a first substrate side and a second set of one or more semiconductor devices on a second substrate side. The multi-die package is located at the first circuit board side. The heat dissipator is located at the second circuit board side, and thermally coupled to the second set of semiconductor devices. One or more portions of the circuit board are removed between the first circuit board side and the second circuit board side so as to define one or more holes through the circuit board and to facilitate thermal coupling between the second set of semiconductor devices and the heat dissipator through the one or more holes.

US Patent:

8456934, Jun 4, 2013

Filed:

Mar 26, 2012

Appl. No.:

13/430450

Inventors:

Scott C. Best - Palo Alto CA, US
Ming Li - Fremont CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

G11C 29/00

US Classification:

365200, 365201

Abstract:

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

US Patent:

20060221573, Oct 5, 2006

Filed:

Apr 4, 2005

Appl. No.:

11/098823

Inventors:

Ming Li - Fremont CA, US

International Classification:

H05K 7/20

US Classification:

361704000

Abstract:

A system for dissipating heat away from multiple semiconductor modules includes a thermal conductor having a thermally conductive base and multiple thermally conductive semiconductor module connectors thermally coupled to the base. Each of the semiconductor module connectors is configured to connect to a different semiconductor module of multiple semiconductor modules.