Ming Chang Tsai

US Patent:

7151502, Dec 19, 2006

Filed:

Dec 29, 2004

Appl. No.:

11/025397

Inventors:

Andy Stavros - San Jose CA, US
Ming Tsai - Sunnyvale CA, US
Stuart E. Wilson - Menlo Park CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01Q 21/00

US Classification:

343853

Abstract:

A phased antenna array is disclosed. The phased antenna array is composed of one or more modules and has a plurality of antenna. The array has a plurality of antenna configured to operate as an array and each module has at least one antenna. The modules have a substrate that supports the antenna, a microelectronic device for sending signals to or receiving signals from said antenna and conductive traces that connect that antenna to the microelectronic device. In those embodiments where the phased antenna array has more than one module, a common substrate supports the one or more modules. A combination of circuitry and interconnects achieves the desired electrical interconnection between the modules.

US Patent:

7489524, Feb 10, 2009

Filed:

Jun 2, 2005

Appl. No.:

11/143201

Inventors:

Ronald Green - San Jose CA, US
Sridhar Krishnan - Campbell CA, US
Stuart E. Wilson - Menlo Park CA, US
James Gill Shook - Santa Cruz CA, US
Ming Tsai - Sunnyvale CA, US
Andy Stavros - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H05K 1/11

US Classification:

361803, 439 44, 439 65, 439 74, 439 85

Abstract:

An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element. The bottom end of the interconnect element abuts the top surface of the first circuit panel and the top end abuts the bottom surface of the second circuit panel, where at least some of the first conductive traces are in conductive communication with the second conductive traces through the interconnect traces.

US Patent:

20130328582, Dec 12, 2013

Filed:

Jun 12, 2012

Appl. No.:

13/494663

Inventors:

Liang Han - Sunnyvale CA, US
Matthew A. Mow - Los Altos CA, US
Ming Tsai - Cupertino CA, US
Thomas E. Biedka - San Jose CA, US
Robert W. Schlub - Cupertino CA, US
Ruben Caballero - San Jose CA, US

International Classification:

G01R 31/00
G01R 31/26
G01R 35/00

US Classification:

32475002, 32475001

Abstract:

A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results.

US Patent:

20190096581, Mar 28, 2019

Filed:

Sep 27, 2017

Appl. No.:

15/717431

Inventors:

- Cupertino CA, US
Ming Y. Tsai - San Jose CA, US
Paul A. Martinez - Morgan Hill CA, US
Scott D. Morrison - Watertown MA, US
Tracey L. Chavers - Los Gatos CA, US

International Classification:

H01G 4/248
H01G 4/30
H01G 4/002
H01G 4/224
H05K 1/02
H05K 1/18

Abstract:

Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.

US Patent:

20190006287, Jan 3, 2019

Filed:

Jun 28, 2017

Appl. No.:

15/636408

Inventors:

- Cupertino CA, US
Ming Y. Tsai - San Jose CA, US
Won Seop Choi - Pleasanton CA, US

International Classification:

H01L 23/552
H01L 49/02

Abstract:

Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.

US Patent:

20180068784, Mar 8, 2018

Filed:

Jan 12, 2017

Appl. No.:

15/405027

Inventors:

- Cupertino CA, US
Ming Y. Tsai - San Jose CA, US
Federico P. Centola - San Jose CA, US
Martin Schauer - Fremont CA, US
Jason C. Sauers - Cupertino CA, US

International Classification:

H01F 27/36
H05K 1/18
H05K 1/02

Abstract:

A system includes a circuit board, an inductor including windings mounted on the circuit board, and a plurality of magnetic field containment devices. Each magnetic field containment device includes an independent electrical circuit that is not directly electrically connected via a conductor to any other magnetic field containment device. Each magnetic field containment device also includes a material of a certain relative permeability. Each magnetic field containment device at least partially surrounds the inductor and, in operation, at least partially contains a magnetic B-Field generated by electrical current in the windings of the inductor. The plurality of magnetic field containment devices, in operation, enables a certain saturation current in the inductor.

US Patent:

20170207024, Jul 20, 2017

Filed:

Jan 18, 2017

Appl. No.:

15/409217

Inventors:

- Cupertino CA, US
Gang Ning - Santa Clara CA, US
Curtis C. Mead - Sacramento CA, US
Ming Y. Tsai - San Jose CA, US
Albert Wang - Sunnyvale CA, US

International Classification:

H01G 4/30
H01G 4/40
H01G 4/224
H01G 4/008
H01G 4/228
H01G 4/012

Abstract:

Methods and devices related to fabrication and utilization of multilayer capacitors presenting low equivalent series resistance (ESR) is illustrated. The capacitors may present electrodes that are coupled to metallic terminations at the bottom and/or at the side of the capacitor. The position of the electrode coupling may lead to smaller current paths in the MLCC electrode, which may decrease line inductances. Methods and systems for fabrication of the capacitors described are also discussed.

US Patent:

20140266470, Sep 18, 2014

Filed:

Mar 17, 2014

Appl. No.:

14/215774

Inventors:

- Greensboro NC, US
Baker Scott - San Jose CA, US
Ming Tsai - Sunnyvale CA, US
Alireza Shirvani - Menlo Park CA, US

Assignee:

RF Micro Devices, Inc. - Greensboro NC

International Classification:

H03F 3/193

US Classification:

330307

Abstract:

This disclosure relates generally to radio frequency (RF) amplification devices and methods of operating the same. In one embodiment, an RF amplification device includes an RF amplification circuit and a stabilizing transformer network. The RF amplification circuit defines an RF signal path and is configured to amplify an RF signal propagating in the RF signal path. The stabilizing transformer network is operably associated with the RF signal path defined by the RF amplification circuit. Furthermore, the stabilizing transformer network is configured to reduce parasitic coupling along the RF signal path of the RF amplification circuit as the RF signal propagates in the RF signal path. In this manner, the stabilizing transformer network allows for inexpensive components to be used to reduce parasitic coupling while allowing for smaller distances along the RF signal path.