Minh Gia Chau

US Patent:

7284143, Oct 16, 2007

Filed:

Dec 29, 2003

Appl. No.:

10/750607

Inventors:

James S. Song - Plano TX, US
Achuta R. Thippana - Plano TX, US
Minh G. Chau - Carrollton TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/04
G06F 1/24
G06F 11/00

US Classification:

713503, 713400, 713401, 713500, 713501, 377106, 327141, 327144, 327152, 327297, 327298

Abstract:

In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay. The method further includes: (1) receiving at a multiplexer the first output signal, the second output signal, and a select control signal indicating which of the first output signal or the second output signal to select; (2) selecting at the multiplexer either the received first output signal or the second output signal based on the select control signal; and (3) generating the selected first output signal or second output signal as a substantially balanced third output signal.

US Patent:

8051313, Nov 1, 2011

Filed:

Apr 28, 2008

Appl. No.:

12/110589

Inventors:

Bixia Li - Plano TX, US
Hugh Mair - Fairview TX, US
Minh Chau - Carrollton TX, US
Alice Wang - Allen TX, US
Uming Ko - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/00
G05F 1/10
H03K 3/02
H03K 17/16

US Classification:

713323, 327198, 327546, 326 21

Abstract:

An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

US Patent:

20060022985, Feb 2, 2006

Filed:

Jul 30, 2004

Appl. No.:

10/903750

Inventors:

Thomas Shepherd - McKinney TX, US
Minh Chau - Carrollton TX, US
Prabha Atluri - Plano TX, US
Sang-Won Song - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 13/18
G09G 5/36

US Classification:

345535000, 345558000

Abstract:

A system comprises a display controller adapted to monitor a first-in, first-out module (“FIFO”) data level, a memory controller coupled to said display controller, and a memory coupled to said display controller and said memory controller. The memory controller permits the display controller to immediately access the memory when the FIFO data level drops below a pre-determined threshold level and no display panel horizontal or vertical blanking periods are in progress.