Minli Lin

US Patent:

8594854, Nov 26, 2013

Filed:

Mar 15, 2011

Appl. No.:

13/048710

Inventors:

Ali Ahmad Tareen - Milpitas CA, US
John R. Hupton - San Jose CA, US
Minli Lin - Saratoga CA, US
Krishna Kumar Vavilala - Cedar Park TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G05D 3/12
G05D 5/00
G05D 9/00
G05D 11/00
G05D 17/00
G05B 11/01
G06F 1/00

US Classification:

700295, 700 22, 700286, 700291, 700297, 713300, 713321, 713340

Abstract:

In accordance with an example embodiment, there is disclosed herein a technique for the formation of power sharing groups by a power supply module. The power supply module sends a discovery message and eventually receives the discovery message back. The power supply message also receives a discovery message from at least one other power supply module. The power supply module determines whether it is a master of the group, and if the power supply module is the master of the group, the power supply module determines power budgets for the at least one other power supply module. After obtaining a power supply budget, a controllable switching device is closed enabling power to be shared with the at least one other power supply module.

US Patent:

20210089366, Mar 25, 2021

Filed:

Dec 24, 2019

Appl. No.:

16/726492

Inventors:

- Menlo Park CA, US
Neeraj Upasani - Redmond WA, US
Drew Eric Wingard - Palo Alto CA, US
Gregory Edward Ehmann - Sleepy Hollow IL, US
Marco Brambilla - Campbell CA, US
Minli Lin - San Jose CA, US
Miguel Angel Guerrero - Palo Alto CA, US

International Classification:

G06F 9/52
G06F 9/54
G06F 9/30
H04N 13/344

Abstract:

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.